VHDL language application example guide

An identifier in VHDL can be a constant, variable, signal, port, subroutine, or parameter name. The following rules apply when using identifiers:

Identifiers consist of letters (A…Z; a…z), numbers, and the underscore character.

Any identifier must start with an English letter.

The last character cannot be an underscore.

Two consecutive underscores are not allowed.

· Identifiers are not case sensitive.

VHDL-defined reserved words or keywords cannot be used as identifiers.

Comments in VHDL begin with two consecutive dashes (--) and continue until the end of the line.

The following are illegal identifiers:

-Decoder — cannot start with a non-English letter

3DOP — cannot start with a number

Large#number — "#" cannot be part of an identifier

Data__bus — cannot have double underscores

Copper_ — The last character cannot be an underscore

On —Keyword cannot be used as an identifier.

Note: Identifiers in AHDL are case-sensitive, but in VHDL they are not. So when writing programs, you must develop good writing habits, use uppercase when using keywords, and use lowercase when defining your own identifiers.

The detailed descriptions of several data objects represented by identifiers are as follows:

1) Constant

A constant is a fixed value, mainly to make constants in design entities easier to read and modify. Once a constant is assigned, it cannot be changed. General format:

CONSTANT constant name: data type: = expression;

Example: CONSTANT Vcc: REAL: =5.0;

—Design entity power supply voltage specification

The value assigned to the constant should be consistent with the defined data type.

The scope of use of a constant depends on where it is defined. Constants defined in a package have the greatest global characteristics and can be used in all design entities that call this package; constants defined in a structure in a design entity can only be used in this structure; constants defined in a unit in a structure, such as a process, can only be used in this process.

2) Variable

A variable is a local variable. It can only be used in process statements, function statements, and process statement structures. It is used as local data storage. During the simulation process, unlike signals, which are assigned values ​​only at the specified simulation time, variable assignments take effect immediately. Variables are often used in assignment statements to implement certain algorithms.

General format:

VARIABLE variable name data type constraints: = expression;

Example: VARIABLE x,y:INTEGER; —define x,y as integer variables

VARIABLE count: INTEGER RANGE0 TO255:=10; —Define the range of the count variable

The scope of application of a variable is limited to the process or subroutine in which the variable is defined. If the variable is used outside the process, the value must be assigned to a signal of the same type, that is, the signal used to transfer data between processes.

The syntax of the variable assignment statement is as follows:

Target variable:=expression;

The variable assignment symbol is ":=". The expression on the right side of the assignment statement must be a value of the same data type as the target variable. Variables cannot be used for hardware wiring and storage components.

3) Signal

Signal is the basic data object that describes the hardware system. It is similar to a connecting line. Except for the lack of data flow direction, its other properties are consistent with the concept of the entity's port. The value of a variable can be passed to a signal, but the value of a signal cannot be passed to a variable. Signals are usually described in constructs, package collections, and entities. The signal description format is:

SIGNAL signal name: data type;

Setting the initial value of the signal is not necessary, and the initial value is only valid in VHDL behavioral simulation.

1. Variables

Variables can only be used in processes, functions, and procedures, and take effect immediately once assigned.

Example: VARIABLE x, y: INTEGER;

VARIABLE count: INTEGER RANGE 0 TO 255:=10;

2. Signal

The concept of a signal is almost the same as that of a port, except that it has no direction.

Example: SIGNAL sys_clk: BIT:='0';

SIGNAL ground: BIT:='0'

In the program, the signal value is input using the substitution operator "<=" instead of the assignment operator ":=", and the signal can be added with a delay.

Signal sending statement:

s1<=s2 AFTER 10ns

A signal is a global variable that can be used for communication between processes.

3. The difference between signals and variables:

Signal assignment can have a delay time, while variable assignment has no time delay;

In addition to the current value, a signal has many related values, such as historical information, while a variable only has the current value;

Processes are sensitive to signals but not to variables;

Signals can be global to multiple processes, but variables are visible only in the order in which they are defined;

A signal can be thought of as a wire in hardware, but there is no such correspondence for variables.

Example: ENTITY reg1 IS

PORT ( d : in BIT;

clk : in BIT;

q : out BIT);

END reg1;

ARCHITECTURE reg1 OF reg1 IS

SIGNAL a, b : BIT;

BEGIN

PROCESS (clk)

BEGIN

IF clk='1' AND clk'event THEN

a <= d;

b <= a;

q <= b;

END IF;

END PROCESS;

END reg1;

ENTITY reg1 IS

PORT ( d : in BIT;

clk : in BIT;

q : out BIT);

END reg1;

ARCHITECTURE reg1 OF reg1 IS

BEGIN

PROCESS (clk)

VARIABLE a, b : BIT;

BEGIN

IF clk='1' AND clk'event THEN

a := d;

b := a;

q <= b;

END IF;

END PROCESS;

END reg1;