Design of SOPC Technology Based on DSP

3 System Hardware Design

The hardware system of the system consists of three parts: FPGA part, memory part and peripheral components part. The FPGA part is built in the FPGA, and it is this part that needs to be designed in SOPC Builder. It includes a NiosII CPU core, an internal clock, an Avalon bus controller, a JTAG_UART communication module for connecting the download and debugging program of the Nios II core, a DDS interface module and a DDS module, a FIR, IIR digital filter interface module and a functional module, a codec module and an interface module, and a Flash memory module. Its design is different from general embedded development. The corresponding peripheral module core can be added outside the Nios II core (but still in the same FPGA chip), and connected to the Nios II through the on-chip Avalon bus. In order to make the Nios II system with DSP processor function work normally, some control keys are connected to the periphery of the FPGA to schedule the application of each module.

3.1 Building a Nios II Embedded Processor System

First, use Quartus II to build a project, and select the target device as Cyclone EPIC12;
then use SOPC Bider to create a Nios II component model, generate a hardware description file, lock the pins, perform synthesis and adaptation, and generate a Nios II hardware system download file; then build a Nios II embedded system, and add the required components (such as Nios II CPU core, timer Timer, JTAG_UART, Avalon tri-state bus bridge, key input I/O port and Flash, etc.) from the SOPC Buider component column. In addition, in order to realize the read and write access of the NiosII processor to the EPCS Flash memory, an EPCS Serial F1ash Controller component must be added. Through this controller, the SOF file used for FPGA configuration and the software running on the CPU are stored in the EPCS device together, so as to greatly simplify the hardware system composition structure. In order to ensure that the address arrangement of all components is legal, the addresses of each component must be automatically allocated; finally, the whole process compilation (i.e. analysis, synthesis, adaptation and output file assembly) is carried out to complete the design of the Nios II hardware system.

After the Nios II hardware system design is completed, the configuration file is downloaded to the specified FPGA. Through the SOPC Builder software window, you can enter the Nios II IDE software development environment for software design.

3.2 Establishment of DSP processor functional system

Using DSP Bider to design DSP modules on FPGA can achieve high-speed DSP processing. However, in practical applications, in addition to requiring high DSP speed, the algorithms processed by DSP are often complex. If DSP Bider is used alone to implement pure hardware DSP modules, it will consume too many hardware resources, so sometimes it is impossible to complete many models with complex algorithms. Nios II is an embedded microprocessor soft core built on FPGA, and one of its important features is that it has custom instructions.

In DSP algorithms, some operations (such as complex multipliers, integer multipliers, floating-point multipliers, etc.) will appear repeatedly, but there are no relevant instructions specifically used for complex multiplication and floating-point multiplication in general-purpose CPUs. In system design, use MATLAB, DSP Buider or VHDL to design and generate hardware modules such as complex multipliers, integer multipliers, and floating-point multipliers. After making some corrections to the above files in the Quartus II environment, customize them to corresponding instructions in the SOPC Buider window, and set or modify the clock cycle for executing the instruction. When performing DSP algorithm operations, these custom instructions can be used for embedded programming through assembly or C language, or even C++ language.

According to the algorithm of complex number operation, assuming there are two complex numbers a+bj and c+dj, the multiplication can be expressed as:

Figure 2 is a complex multiplier model designed using MATLAB and DSP Builder. It implements a 16-bit complex multiplication, where both the imaginary and real parts are 16 bits, and a 32-bit value can be used to represent the complex number. In the design, NiosII is 32-bit data, which can hold exactly two complex numbers.

To set up this complex multiplier hardware module to the corresponding instructions, you must also do the following:

① Click the SignalCompiler icon to convert it, select the device (use Cyclone) and Quartus II synthesizer. After conversion, it will generate the PTF file of SOPCBuider.

② After exiting MATLAB, modify the top-level VHDL file of the complex multiplier generated after conversion in the Quartus II environment. Double-click the CPU item in the SOPC Builder window to enter the "Instruction Addition" editing window and set this hardware module to a custom complex multiplication instruction.

After the instruction is generated, you can use Quartus II to edit the C program for testing; after the test is successful, you can use the complex multiplication instruction when you encounter complex multiplication in the DSP algorithm calculation. This method generates instructions from commonly used hardware modules and implements more complex DSP algorithms in FPGA through a design method that coexists software and hardware. It can combine the flexibility of software and the high speed of hardware, and better solve many problems in modern DSP design. However, for the DDS module, it is still solidified in the FPGA in the form of hardware. Amplitude, phase and frequency modulators can be designed using DDS as needed.

In addition, the peripherals of Nios II can be customized arbitrarily. All the peripherals of Nios II system are connected to Nios II CPU through Avalon bus. Avalon bus is an on-chip bus with relatively simple protocol. Nios II exchanges data with the outside world through Avalon bus. In this system, the AvalonSlave peripheral method is adopted to add the customized AvalorL bus component A/D conversion interface module and D/A interface module to control the sampling A/D work and the waveform data output of high-speed D/A; while the customized Avalon bus component DDS module interface and DSP function conversion control interface are used for Nios II CPU to control the DDS module and to control the selection of DSP function through external keyboard.

Conclusion

The entire system is in a single FPGA programming chip except for the A/D, D/A converter and the control selection keyboard. Because NiosII is used as the CPU, it is possible to customize instructions and various interface module components through the Avalon bus, making the entire DSP system flexible and diverse, and it has more and more applications in modern DSP technology.