Design of Taxi Fare Metering System Based on FPGA

Abstract: Taxi fare collection systems are mostly controlled by single-chip microcomputers, which are easy to be modified and have a high failure rate. To address this problem, a taxi fare collection system based on FPGA is designed, which can simulate the process of car driving, pausing, waiting, stopping, etc., and can display the amount and total distance of the ride at the same time. The design adopts a hierarchical design method, uses VHDL language for programming, and the development software is MAX+plusⅡ. After testing, the waveform and simulation results meet the design requirements.
Keywords: taxi fare collection system; VHDL language; MAX+PLUSⅡ; FPGAWith

the improvement of urbanization and the improvement of people's living standards, taxi services are becoming more and more important. Therefore, taxi meters have come into being. Taxi meters are a special measuring instrument that is installed on taxis to indicate the number of passenger mileage and the total amount of fees that passengers should pay.
Most taxi fare collection systems are controlled by single-chip microcomputers, but they are easy to be modified privately, and the failure rate is relatively high, and it is not easy to upgrade; FPGA has the characteristics of high density, programmability and strong software support, so the designed product has the characteristics of strong function, high reliability and easy modification.
This article designs a taxi fare system based on FPGA, which can intuitively display the mileage of the taxi and the fees to be paid by the passengers.

1 System Function Design
The fare standard of the designed meter is: when the car travels within 3 km, only the starting price of 9.0 yuan is charged; after the car travels more than 3 km, it is charged at 2 yuan per kilometer. After the driving distance reaches or exceeds 9 km, the fare starts to be charged at 3.0 yuan per kilometer. When the car encounters a red light or stops in the middle, 0.5 yuan is charged every 3 minutes. If it stops (rst), the fare is reset and waits for the next billing to start. It is required to be able to display the mileage and the fees to be paid by the passengers, where the mileage is accurate to 0.01 km and the fees to be paid by the passengers are accurate to 0.1 yuan. The display range is: mileage is 0 to 99.99 kilometers, and the fee is 0 to 999.9 yuan.

2 System Design Scheme
The composition of the taxi fare system based on FPGA is shown in Figure 1. It consists of three parts: external input, FPGA control part and digital display. The FPGA part is composed of a frequency division module, a pricing module, a BCD conversion module, and a dynamic decoding scanning module; the external input includes a start button (start), a pause button (pause), a stop button (stop or rst), and two pulse signals (respectively, a distance pulse signal pulse with a pulse every 20 m and a 32 MHz working pulse signal clk32M). The display module uses 8 LED digital tubes to display the mileage and fare respectively. The mileage is displayed in 2 digits and 2 decimals, and the fare is displayed in 3 digits and 1 decimal.

3 Design of each module
Design the FPGA control part, including the control pricing module, BCD conversion module, dynamic scanning decoding module and frequency division module. Adopting the hybrid design method, each sub-part is programmed with VHDL, and the top part is designed with schematic diagram.
3.1 Control pricing module (jijia)
The control pricing module consists of mileage charging module, waiting charging module and total price module.
The mileage charging module mainly counts the pulse signal pulse of the sensor kilometer (one pulse every 20m) to calculate the distance traveled by the taxi in this transaction and the mileage fee. Every 50 pulses count as 1 km, and the total distance is output by the lucheng terminal. Within 3 km, the mileage fare cf1 is 9 yuan unchanged. When it exceeds 3 km, p=1, and the mileage fee counting starts. When the charging stops, that is, the start port is set to "0" or the taxi stops, that is, the rst port is set to "0", the relevant data is reset and cleared.
The waiting charging module starts timing every time when pause=1 after 3 km (p=1). When the number of second pulses reaches 180 (i.e. 3 minutes), the waiting fee cf2 is increased by 5, indicating that the fare is increased by 0.5 yuan.
The total price module adds the mileage charge and the waiting charge to calculate the total fee and output it from the chefei end.
3.2 BCD conversion module (zhuanhuan)
This module converts the fare and distance of the charging module into 4-digit decimal numbers for digital tube display. The input ports acf and bcf are the input ports of the total distance and the total fee respectively. Both are binary codes for decimal coding counting. The encoder generates BCD codes, and the output ports respectively represent the data of units, tens, hundreds, and thousands in BCD codes. Aclk is the working pulse, i.e. 32MHz.
3.3 Dynamic scanning module (dtxianshi)
This module consists of a dynamic scanning module and a decoding module. Dynamic scanning module, this module uses the visual persistence effect and adopts a dynamic scanning circuit to display the 4-digit decimal number of the distance and fare after octal conversion on the digital tube, saving hardware resources and energy. This module displays the distance and fare in turn through the octal scanning module. Port d is the input port of the selected address code, and A1, A2, A3, A4, B1, B2, B3, and B4 are the numerical input ports of ones, tens, hundreds, and thousands respectively. According to the input address code, the module only transmits one digit to the output port q at a time, and outputs the display control signal (dp) of the decimal point at the same time, so that the distance is displayed as 00.00 kilometers and the fare is displayed as 000.0 yuan.
Decoding module, this module translates the BCD code of 0-9 into the digital tube display code. The input port q input scanning module selects the BCD code to be displayed, and the translated digital tube display code is output by g[6. . 0]. The digital tube in this design is a common cathode digital tube.
3.4 Frequency division module (fenp)
The input system clock in this design is 32 MHz, which is divided and then the address of the digital tube is scanned. The input port rse is the taxi stop signal input port. When the taxi stops, the module stops working and is cleared. When the taxi is driving, the input 32 MHz pulse signal is divided, and the second pulse is obtained from the output port cp1, and the 32 Hz working pulse is obtained from cp32.
3.5 Overall circuit
Connect each module according to the input and output relationship, and the top-level circuit schematic is shown in Figure 2. g[6…0] is the seven-segment display code output, which controls the display of 8 digital tubes in turn through dynamic scanning, and dp is the decimal point.

4 System simulation verification
The timing simulation of each submodule and the top-level schematic diagram was performed using MAX+plusⅡ software, and the simulation waveform is shown in Figure 3.

The simulation diagram of the control pricing module is shown in Figure 3. As shown in Figure 3 (a), when reset = 1, start = 1, and pause = 0, it means that the taxi is in the driving state. At this time, the distance begins to increase. When it does not exceed 3 km, the fare is 5A, that is, 90, and the starting price is 9.0 yuan. As shown in Figure 3 (b), after exceeding 3 km, the fare increases by 20 (that is, 2 yuan) for every 1 km traveled. As shown in Figure 3 (c), when reset = 1, start = 1, and pause = 1, the taxi is in the waiting state. At this time, the distance no longer increases, but the time increases. When the time reaches 3 minutes, the fare increases by 5 (that is, 0.5 yuan).
The simulation diagram of the top circuit is shown in Figure 4. It can be seen from the figure that with the change of the input, the common cathode digital tube display code is output from g [6 ... 0], and dp is also at the corresponding digital tube, outputting a high level to light up the decimal point. In summary
, the software simulation results of this design are correct and meet the design requirements.