DDS design based on DSP Builder and its FPGA implementation-EEWORLD

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　　Direct digital synthesizer is a new frequency synthesis technology using digital technology. It generates signals of various frequencies by controlling the step size of frequency and phase increments. It has a series of advantages; high frequency resolution; it can achieve fast frequency switching; it can maintain phase continuity when the frequency changes; it is easy to realize numerical control modulation of frequency, phase and amplitude, etc. Currently, DDS can be implemented using dedicated chips or programmable logic chips [1]. The signal waveforms, functions and control methods generated by dedicated DDS chips are fixed and often cannot meet specific needs [2]. Programmable logic devices have the characteristics of large device scale, fast working speed and programmable hardware. They have a short development cycle and are easy to upgrade, so they are very suitable for implementing DDS.

　　1 How DDS works

　　The structural principle diagram of DDS is shown in Figure 1. DDS uses a numerically controlled oscillator to generate sine waves with controllable frequency, phase and amplitude [3]. The circuit includes a phase accumulator, phase modulator, sinusoidal ROM lookup table, reference clock source, D/A converter, etc. The first three are the digital parts in the DDS structure and have the function of numerically controlled frequency synthesis.

　　The core of the DDS system is the phase accumulator, which completes the phase accumulation process. Under the control of the reference clock, the frequency control word is accumulated by the accumulator to obtain the corresponding phase data. The phase modulator receives the phase output of the phase accumulator and is mainly used for phase modulation of the signal. The output data is used as a sampling address to find Address the sine ROM lookup table to complete the phase-amplitude conversion and output different amplitude codes; then pass through the D/A converter to obtain the corresponding staircase wave; finally, smooth the staircase through the low-pass filter to obtain the frequency control word Determined by the continuous transformation of the output sine wave.

　　2 Design based on DSP Builder and DDS

　　2.1 Introduction to DSP Builder

　　DSP Builder is a system-level tool for DSP development launched by Altera Corporation in the United States. As a Simulink toolbox of Matlab, it allows the design of DSP systems using FPGA to be completely modeled and system-level simulated through the Simulink graphical interface. The design model can Directly convert to VHDL hardware description language, and automatically call EDA design software such as Quartus II to complete synthesis, netlist generation, device adaptation and even FPGA configuration download, making the system description and hardware implementation organically integrated into one, fully embodying the modern electronics Characteristics and advantages of technical automation development.

　　2.2 DSP Builder design principle and parameter settings

　　The DDS system based on DSP Builder is shown in Figure 2 and Figure 3. The DDS subsystem Subsystem has three inputs, namely Freqword (32-bit frequency control word), Phaseword (32-bit phase control word), and Amp (10-bit amplitude control word); one output, the 10-bit DDSOut output. The two Parallel Adder Subtractors are phase accumulator and phase modulator respectively, and the LUT is a sinusoidal ROM lookup table. Set the simulation stop time of Simulink to 5 and the simulation step Fixed Step Size to le-3. Figure (4) corresponds to the output waveform of the DDS system when the frequency, phase and amplitude control words are 4000000, 0 and 10 (parameter 1) respectively. Figure 5 corresponds to the frequency, phase and amplitude control words are 9000000, 500000000 and 15 (parameter 2) respectively. ) is the output waveform of the DDS system.

　　3 DDS design based on FPGA

　　3.1 FPGA implementation of DDS

　　Matlab/Simulink compiles the designed DDS system, and can directly generate QuartusⅡ project files by calling the SignalCompiler tool of DSP Builder, and then calls QuartusⅡ to complete synthesis, netlist generation and adaptation, until the FPGA configuration download process is completed.

　　The FPGA chip used in this design is Altera's Cyclone series chip EP1C6Q240C8. Its capacity is 6,000 logic macro cells, which is equivalent to a standard 150,000 logic gate circuit. The speed is -8. DDS can be realized through a single chip circuit. The phase accumulation and phase modulator are both 32 bits. The sine ROM lookup table stores 1024×10b waveform data. The system clock is 55.6MHz. The FPGA can be used to easily implement various complex frequency modulation, phase modulation and amplitude modulation functions as needed. It has Wasted real-time.

　　3.2 Simulation results

　　Use QuartusⅡ to simulate the project files generated by DSP builder. For the DDS system with different parameter settings, the simulation waveforms are shown in Figure 6 and Figure 7.

　　In the figure, clock is the system clock, sclrp is the high-level reset signal, iFreqwords, iPhasewords and iAmps are the input frequency, phase and amplitude control words respectively, and oDDSOut is the output signal. When the reset signal sclrp arrives, 0 is assigned to the phase accumulator and an initial phase value is assigned to the phase modulator. Under the control of the clock signal, the frequency control word controls the accumulation of the phase accumulator. The phase modulator performs phase modulation, and its output The data is addressed as a sampling address to the ROM lookup table, and a continuous sine wave signal can be output on the oDDSOut pin. Under different parameter settings, the simulation results in QuartusⅡ are basically consistent with the simulation results in Matlab/Simulink in terms of phase, frequency and amplitude. FPGA can output higher-quality signals. Although the internal digital signal has a certain amount of jitter, the error can usually be kept within the allowable range by using jitter injection technology, delay superposition method, etc. [3].

　　4 Conclusion

　　The method of using programmable logic chips to design DDS is usually to use a combination of VHDL language input and schematic diagram method to design the entire signal generation circuit. This method usually requires the use of many modules, is highly comprehensive, and has high requirements for designers. This article uses DSP Builder, the interface tool between QuartusⅡ and Matlab/Simulink, to design the entire DDS system. DSP Builder has a friendly development environment, is highly interactive with QuartusⅡ, and is easy to use. Designers only need to briefly understand the VHDL description language to directly call the established Matlab and Simulink design processes, conduct modeling and system-level simulation through the Simulink graphical interface, and then call Quartus II for synthesis, netlist generation and Adaptation, and finally completes the configuration download process to the FPGA. The entire design idea is flexible, the graphical interface is simple and intuitive, and the development cycle is short. The simulation results show that the design scheme is correct in principle and effective. Using FPGA to implement DDS is more flexible than a dedicated DDS chip. As long as the data and control parameters in the ROM in the FPGA are changed, DDS can generate arbitrary modulation waveforms with high resolution and considerable flexibility. Embedding DDS design into a system composed of FPGA chips will not increase the system cost much, while the price of purchasing dedicated chips is many times that of the former. Therefore, using FPGA to design a DDS system is very cost-effective.

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