A DSP-based software phase-locked loop model and implementation

　　With the development of large-scale integrated circuits and high-speed digital signal processors, signal processing in the communications field is increasingly implemented in the digital domain. Software phase locking technology is a research . The phase-locked technology used in software radio receivers is based on the implementation of digital signal processing technology on general programmable . Since the functions of this type of phase-locked loop are mainly implemented through software programming, it can be called It is a software phase-locked loop ( software PLL) ^[1] .
   
　　Although the basic algorithm idea used by software phase-locked loops has not changed much compared with analog phase-locked loops and digital phase-locked loops, their implementation methods are completely different. This article will establish the Z-domain model of the software phase-locked loop and analyze the delay estimation , acquisition speed and software phase-locked loop model issues under multi-rate conditions in the software phase-locked loop ^[1] . 

1 Basic model of software phase-locked loop
   
　　Based on the analog phase-locked loop, the Z-domain model of the software phase-locked loop is established using the connection between digital and analog systems, taking the second-order type-2 phase-locked loop as an example. Literature [2] gives the basic model and principle of phase-locked loop in detail.
   
　　If the basic components of the phase-locked loop are implemented in the form of software programming, the basic components of the software phase-locked loop can be obtained, as shown in Figure 1.
   
　　Firstly, starting from the S-domain model of the analog phase-locked loop, the Z-domain model of the software phase-locked loop is obtained (for the S-domain model please refer to the literature [ 2]). Since bilinear transformation is an important method to connect analog systems and digital systems, with the characteristics of simple transformation and clear expressions ^{[ 3]} , this paper chooses the bilinear transformation method as one of the two methods between analog phase-locked loopsbasis for conversion. 

Equation (1) is the complex frequency domain expression of the bilinear transformation method:

where: T is the sampling time interval connecting the digital system and the analog system, and 1/T represents the sampling frequency. According to this conversion relationship , the digital complex frequency domain expressions corresponding to each part of the S domain model are converted, and the complex frequency domain model shown in Figure 2 can be obtained. 

In practical applications, second-order linear systems are often described by the damping factor ξ and the undamped oscillation frequency ω _n . In the second-order type-2 phase- locked loop, the corresponding relationship between τ ₁ , τ ₂ , K and ξ, ω _n

    is as follows: On the basis of equation (1) and equation (2), perform equivalent transformation on Figure 2, Another linear phase Z-domain model , as shown in Figure 3. 

In model I, the parameters τ ₁ , τ ₂ and K are closely related to the resistors, capacitors and voltage-controlled oscillators that implement the circuit function . The software phase-locked function is realized by multipliers, adders and registers, so it is more practical to use Model II to characterize the linear phase Z-domain model of the software phase-locked loop. 
2 Mathematical model of software phase-locked loop
    The Z-domain model of the digital phase detector is as follows:
 
    One of the methods to realize the digital phase detector is to use the orthogonal decomposition of the signal. Figure 4 is the principle block diagram of this method. 

Among them: LPF represents low-pass filtering, and A is the constant gain brought by the low-pass filter. Therefore, the output of the phase detector:

    After inverse Z transformation, the time domain expression of the digital loop filter is obtained:

    Through inverse Z transformation, the time domain expression of the numerically controlled oscillator is obtained:

    The variable u _c (nT) has a small value and does not change will be too fast, so Equation (14) is established:

    Combining Equation (11), Equation (12) and Equation (13), the expression of the NCO output signal is obtained: If the

numerically controlled oscillator is described in terms of digital frequency, it is called its digital center The frequency is ω ₀ T and the digital offset frequency is ω _n ² ·u _c (nT) ·T. Therefore, the sensitivity and digital sensitivity of the numerically controlled oscillator are ·T respectively . 3 Software phase-locked loop under multi-rate conditions　　In digital receivers, sampling rate conversion problems under multi-rate conditions are often encountered. The so-called multi-rate system refers to the existence of 2 or more sampling rates in a digital system ^[4] . The mixers that make up the software phase-locked loop phase detector usually work at the system sampling frequency. Under the premise of satisfying the Nyquist sampling law, the system sampling rate of a digital receiver is generally as high as several 10 M. As for the arctangent table that is part of the digital phase detector, since the data after mixing has been extracted multiple times, the operating frequency has dropped to a level similar to the signal baud rate. Data extraction also reduces the computational complexity of the DSP. The processing speed of the loop filtering completed is approximately equal to the signal baud rate. In addition, since the numerically controlled oscillator in the software phase-locked loop needs to provide the mixer with the same rate of orthogonal carrier, its operating rate is equal to that of the mixer, and interpolation is required to adjust the rate. 　　In order to make reasonable use of the limited computing resources of the DSP, the working rate of the loop filter is always reduced as much as possible while meeting the synchronization needs , which is commonly referred to as the loop frequency. The loop frequency is an important parameter of the software phase-locked loop. It also determines the calculation amount and acquisition speed of the phase-locked loop algorithm. If the loop frequency is too high, it will bring additional computational burden. If the loop frequency is too low, it cannot meet the needs of capture speed. In applications, the system baud rate is usually used as the loop frequency. The linear phase Z-domain model corresponding to this extended model is shown in Figure 5. 


    

   

Among them: D represents data extraction, and I represents data interpolation. Anti-aliasing filtering must be performed before data is extracted. FIR filters that can be used for anti-aliasing filtering include CIC filters, half-band filters, etc.
   
　　In practical situations, zero-order preserving interpolation requires almost no additional computation, so it is often used. In fact, the loop frequency f _L can always keep up with the rate of change of the loop filter output signal. In other words, sampling the loop filter output signal at a rate of f _L retains all its information, so zero-order maintaining interpolation will not have much ^{[ 4]} .
   
　　Combined with the basic principles of the software phase-locked loop mentioned above, let's use Matlab simulation to observe the system response of the software phase-locked loop. This article uses the frequency step signal as input to observe the system response of the software phase-locked loop to further verify a series of software phase-locked loop models established in this article.
   
　　The system sampling frequency is set to 1 MHz, the simulation time is 0.1 s, the signal center frequency is 125 kHz, the starting phase is -π/4, the input frequency step is 100 Hz, the starting point is 0.02 s, and the decimation factor is 8. Under normal circumstances, it is expected that the loop works in an under- damped state, and the damping factor ξ =0.707 is taken. ω _n is determined by 2πΔF (fast capture bandwidth) ^[2] , and is taken as 2π*40, 2π*50, and 2π*100 respectively . The phase error response curve, NCO bias frequency curve and phase curve of the frequency step signal are simulated, as shown in Figure 6.
   
It can be seen 　　from Figure 6 that the phase error of the software phase-locked loop is 0 in the interval [0, 0.02] and is in a locked state. At t=0.02 s, the input signal frequency produces a step of 100 Hz, causing the software phase-locked loop to enter the acquisition process. Due to the correction effect of the software phase-locked loop, when ω _n =2π*50, the system re-enters the synchronization state at t=0.05 s, and the phase error is still 0. It can be seen from the phase error response curve that the phase-locked loop can track the frequency . It also shows that although the phase-locked loop phase detection error is 0, its output The signal is not 0, and the 100 Hz bias frequency generated by this control signal ensures that the NCO output is synchronized with the input signal. When the fast capture bandwidth changes, the capture speed of the phase-locked loop also changes. The wider the fast capture bandwidth, the faster the capture speed. 

4 DSP implementation of software phase-locked loop
   
　　In the implementation of wideband digital receiver, the universal programmable down-converter HSP50214B is used for digital down-conversion. In the entire feedback loop that implements carrier synchronization and symbol synchronization software phase-locked loop, the numerically controlled oscillator and phase detector are completed by HSP50214B, and the loop filtering is completed in TMS320C6X. The DSP implementation block diagram is shown in Figure 7.



    Loop delay is a factor that should be taken seriously. There are two main reasons for software phase-locked loop loop delay:
    (1) Delay caused by the FIR filter in the loop;
    (2) Additional delay caused by data waiting for processing.
   
　　In a digital receiver, two levels of coarse synchronization and fine synchronization are used. The coarse synchronization loop has a large delay and a slow response speed; the fine synchronization loop has a small delay and a fast response speed. Coarse synchronization ensures that the effective signal falls within the passband of the filter. Fine synchronization can obtain greater accuracy based on coarse synchronization. Capture belt and timing belt. In addition, several sampling points are discarded to eliminate unnecessary loop delays.
   
　　It can be seen that the software phase-locked loop has the advantage of flexible processing. It gets rid of complex hardware circuit design and solves many problems encountered in analog loops. At present, as DSP functions become more and more powerful and the working speed becomes higher and higher, necessary conditions are created for the development of software phase locking technology. 

references

［1］Best RLPhase locked loops design simulation and application ［M］. 3rd EditionMcGraw Hill, 1997
［2］Zhang JueshengPhase locked technology［M］. Xi’an: Xi’an University of Electronic Science and Technology Press, 1994
［3 ] Ding Yumei Digital Signal Processing [M]. Xi'an: Xi'an University of Electronic Science and Technology Press, 1995 [
4 ] Zong Kongde Multiple Sampling Rate Signal Processing [M]. Beijing Tsinghua University Press, 1996
[ 5] HARRIS Company, The principle and application of HSP50214B
［6］John Proakis GDigital communications［M］. Beijing: Electronic Industry Press , 1999