Design and implementation of communication between multi-channel synchronous sampling ADC (AD7606) and floating-point DSP (ADSP-21479) in power system

1.1 Introduction to AD7606
AD7606 is a 16-bit, 8-channel synchronous sampling analog-to-digital data acquisition system. AD7606 fully meets the requirements of the power system and has flexible digital filters, 2.5V reference voltage source, reference voltage buffer, and high-speed serial and parallel interfaces. It uses a single 5V power supply and can process ±10V and ±5V true bipolar input signals. At the same time, all channels can be sampled at a throughput rate of up to 200kSPS.

Figure 1 Internal principle block diagram of AD7606.

Figure 2 Pin diagram of AD7606.
• AVcc analog power supply, 4.75V~5.25V
• Vdrive logic part power supply
• Vdd analog input part positive voltage
• Vss analog input part negative voltage
• DGND digital ground
• AGND analog ground

1.2 DSP-21479" title="ADSP-21479">ADSP-21479 Introduction
ADSP-21479 is a member of the SIMD (Single Instruction Multiple Data) SHARC family. It is based on the latest 65nm process and has the characteristics of low cost and low power consumption. It is a 32/40-bit floating-point DSP integrated with large-capacity on-chip SRAM and ROM. ADSP-21479 has excellent performance, 266MHZ/1596MFLOP:

• 266 MHz/1596FLOPS SIMD SHARC core, supporting 32-bit floating point, 40-bit floating point and 16/32-bit fixed point data types
• Supports up to 5 Mb of on-chip SRAM
• Supports 16-bit wide SDR, SDRAM memory interface
• Digital application interface DAI, supports up to 8 high-speed synchronous serial ports (SPORT) and SPI serial ports
• 2 precise clock generators
• 20-line digital I/O ports
• 3 timers, UART, I2C compatible interface
• ROM/JTAG security mode
• Available in 196-pin CSP_BGA package and 100-pin LQFP package products, suitable for industrial customers’ requirements
• Available in commercial, industrial temperature and automotive temperature grades

Figure 3 Internal block diagram of the ADSP-21479.

2. Configuration and connection of AD7606 and ADSP-21479
The power supply of AD7606 chip adopts single 5V power supply, as shown in Figure 4:

Figure 4. AD7606 power supply diagram.
AD7606 adopts hardware configuration method, and the specific configuration is as follows:
1) When RANGE=0 is set, the analog input range is ±5Vref.
2) Set /PAR /SER/BYTE SEL to high level and select serial mode.
3) CONVSTA, CONVSTB, use the same source excitation.
4) Set REF SELECT=0, use external reference voltage

SHARC ADSP-21479 SRU settings:
SPORT0_SCLK  DAIP 1
SPORT0_FS  DAIP 4
SPORT0_DA  DAIP 5
FLAG4  DPI_PIN1
FLAG5  DPI_PIN2
According to the above configuration, the system diagram of ADSP-21479 connecting with AD7606 through SPORT port is shown in Figure 5:

Figure 5 Schematic diagram of hardware connection between AD7606 and ADSP-21479 in serial mode

3. Timing Analysis
The working timing of AD7606 is shown in Figure 6. The FLAG signal of DSP drives the CONVST A/B signal to start the conversion process. BUSY indicates the working state and is connected to the interrupt input of DSP. When BUSY is high, it indicates that it is in the conversion state. After the conversion is completed, the falling edge from high to low causes the DSP to interrupt. In response to the interrupt, DSP reads the converted data of 8-channel ADC through SPORT0.

Figure 6 AD7606 serial data read timing

The timing of the ADSP-21479 SPORT port is shown in Figure 7. After the FS signal is activated, the data is read with the clock beat. We choose the SPORT data width to be 32 bits, so four FS signals can read the data of eight channels.

Figure 7 ADSP-21479 SPORT serial data reception timing [page]

4. Test results and conclusions
The DSP software sets a 50K sampling signal and samples the data of 8 channels simultaneously. The input signals of each analog channel are: channel 5 is connected to a 1KHz sine wave, and the other channels are grounded.
4.1 Test results
1) Use the plot window of VDSP5.0++ (VDSP->View->Debug Windows->Plot) to observe the 5-channel data.
1. Channel 5 extracts a 1KHz sine wave;

4.2 Conclusion
This connection method uses only one serial SPORT port of the DSP to read the data of 8 ADCs at the same time. However, since all 8 data are output to the DSP through one data output, and the highest serial clock frequency supported by AD7606 is limited, the analog-to-digital conversion also takes up a part of the sampling cycle. Therefore, under the serial output connection, AD7606 cannot work at the highest sampling rate of 200KSPS.
According to the AD7606 data sheet, the upper limit of SCLK of AD7606 is 23.5MHz. The FLAG signal drives the CONVST A/B signal, and a single serial output of eight channels of data. Without considering the conversion time, the highest sampling rate can reach 23500000/(16×8)=183.5kHz. Since each cycle data conversion will consume a certain amount of time, this speed cannot be achieved in practice. Assuming that the sampling period is represented by Tconvst, according to the AD7606 data sheet, the analog-to-digital conversion time is 3.45us, so Tconvst-3.45us represents the time for transmitting data in the sampling period. The total data volume of eight channels is 128 clock cycles, so (Tconvst-3)/128 is approximately the clock cycle of each bit of data. Since the maximum SCLK is 23.5MHz, the maximum sampling frequency in this mode can be calculated:
(Tconvst(max)-3.45)/128 = 1/23.5
Tconvst(max)≈8.89us
, that is, the maximum sampling rate is 1/ Tconvst(max) = 112KSPS.
Similarly, if two ports are used to output conversion data at the same time, that is, two SPORTs are started to read the data of 8 channels respectively, the actual maximum sampling rate can reach 161K SPS.

When AD7606 outputs to DSP in parallel, the highest sampling rate of 200KSPS can be obtained.
5. DSP Reference Code
1. Configure SRU
// This function will setup the SRU Registers
void InitSRU(void)
{
//Generating Code for connecting : SPORT0_CLK to DAI_PIN1
SRU (HIGH, PBEN01_I);
SRU (SPORT0_CLK_O, DAI_PB01_I);

//Generating Code for connecting: SPORT0_FS to DAI_PIN4
SRU (HIGH, PBEN04_I);
SRU (SPORT0_FS_O, DAI_PB04_I);

//Generating Code for connecting: DAI_PIN5 to SPORT0_DA
SRU (LOW, PBEN05_I
); SRU (DAI_PB05_O, SPORT0_DA_I);

//Generating Code for connecting: FLAG4 to DPI_PIN1
SRU (HIGH, DPI_PBEN01_I
); SRU (FLAG4_O, DPI_PB01_I);

//Generating Code for connecting: FLAG5 to DPI_PIN2
SRU (HIGH, DPI_PBEN02_I
); SRU (FLAG5_O, DPI_PB02_I);

}
2. IRQ1 BUSY interrupt service routine
void AD7606_BUSY_IRQs(int sig_int)
{
busy++;
interrupt(SIG_SP0,Count_SPORT0_RX_IRQs);
#ifdef DMA
* (volatile int *)SPCTL0 =( SPEN_A | SLEN32 | ICLK | IFS | LAFS | SDEN_A | FSR | DITFS| LFS );
#endif
#ifdef CORE
* (volatile int *) SPCTL0 =( SLEN16 | ICLK | IFS | FSR | LAFS | LFS | DITFS);
*(volatile int *) SPCTL0 |=SPEN_A ;
#endif
}
3. SPORT initialization routine
void init_sport(){
* (volatile int *) SPCTL0 = 0;
* (volatile int *) SPCTL1 = 0;
* (volatile int *) SPMCTL0 = 0;
* (volatile int *) SPMCTL1 = 0;
SPORT_DMA_setup:

* (volatile int *) IISP0A = (int)rx_buf0a ;
* (volatile int *) IMSP0A = 1;
* (volatile int *) CSP0A = CHNUM;

//configure the sport
/* */
/* CLKDIV0=[fCCLK(266 MHz)/4xFSCLK(17 MHz)]-1 = 0x0005 */
/* FSDIV0=[FSCLK(10 MHz)/TFS(2 MHz)]- 1 = 31 = 0x001F */
//13m hz 1m 0x00080003;
/* Configure SPORT0 as a reciever (Rx) */
* (volatile int *) DIV0 = 0x001F0005;

}
4. SPORT interrupt routine
void Count_SPORT0_RX_IRQs(int sig_int)
{
SP0I_counter++;
#ifdef CORE
rx_buf0a[(SP0I_counter-1)*CHNUM]=(short)(*pRXSP0A);
#endif
* (volatile int *) SPCTL0 =0;
finished =1;
#ifdef DMA

if(SP0I_counter==1024){
* (volatile int *) IISP0A =(int)rx_buf0a ;
SP0I_counter=0;
}
else
* (volatile int *) IISP0A =(int)(rx_buf0a+ (SP0I_counter)* CHNUM);
* (volatile int *) IMSP0A = 1;
* (volatile int *) CSP0A = CHNUM;

#endif
interrupt(SIG_SP0,SIG_IGN);
}