Inverter Inertia Output Technology Based on FPGA

Energy conservation and consumption reduction is the basic national policy of the country, and energy conservation in power plants is an important part of energy conservation and consumption reduction in the power system. The use of high-voltage frequency conversion technology to carry out technical transformation of the driving power supply of important power-consuming equipment in power plants is an effective way to save energy and reduce consumption in thermal power plants. As high-voltage inverters have been more and more widely used in power plants, the stability and reliability of inverter operation will directly affect the safety of the entire power plant. In actual operation, if the main controller of the inverter crashes or resets, the inverter will stop output and the load motor will stop, which will cause huge losses to the power plant. For the most widely used cascade multi-level inverter, this paper adopts the inverter inertia output technology based on FPGA, that is, when the FPGA detects an abnormality in the main controller, it maintains the output of the inverter according to the memory value until the controller returns to normal, which will greatly improve the stability and reliability of the inverter.

2 Working principle of cascaded multilevel inverter

Cascaded multilevel inverters, also known as unit series multilevel inverters or perfect harmonic-free inverters, achieve high-voltage output by connecting several low-voltage power units in series. The harmonic content of voltage and current is low, the harmonic pollution to the power grid is small, the input power factor is high, and there is no need to use input harmonic filters and power factor converters. They are widely used in practice. Taking a 6kv inverter as an example, each phase is connected in series by 6 power units with a rated voltage of 577v. There are 18 power units in three phases, which are powered by 18 secondary windings of the input isolation transformer. The 18 secondary windings are divided into 3 groups, and there is a 20° phase difference between each group, forming an 18-pulse rectification. The total voltage distortion rate is only 3%, and the total current distortion rate is less than 4%. Its structure diagram is shown in Figure 1.

Figure 1 Cascade 6kv inverter structure diagram

The structure of the power unit is shown in Figure 2. After the three-phase AC is rectified, it is filtered by the filter capacitor to form a DC bus voltage. The inverter consists of four IGBT modules with a withstand voltage of 1700V to form an H-bridge single-phase inverter circuit. Through PWM control, a variable-voltage and variable-frequency AC output is obtained at the output end. The output voltage is single-phase AC 0~577V and the frequency is 0~50Hz. The bypass function is a function that disconnects the fault point when a device fails and allows the device to continue to operate normally. When bypass is required, the thyristor V is turned on to bypass the output of the power unit. During normal normal operation, the thyristor V is in the off state.

Figure 2 Cascade inverter power unit structure diagram

3 Phase-shifted carrier SPWM modulation method based on FPGA

The basic principle of phase shift carrier technology is to use several 1.2kHz triangular carrier signals to compare with a sinusoidal reference signal (per phase) to generate a SPWM signal. By properly shifting the triangular carrier, harmonics of a specific order can be eliminated. Taking phase A as an example, the sinusoidal modulation wave and the triangular carrier are shown in Figure 3. The amplitude and phase of the sinusoidal modulation wave used in the six-stage power unit are the same, while the triangular carrier of each power unit has the same shape but different phases. The phase angle between each carrier is shifted by 2π/6, i.e., 60°, in sequence, so that the output voltage and current change rate can be effectively suppressed. The modulation waves of the left and right bridge arms of the H-bridge unit have opposite phases, which helps to improve the equivalent carrier ratio of the entire system. Experiments have proved that the equivalent carrier frequency when the n-stage unit is connected in series is 2n times the frequency of the triangular carrier, and the DC voltage utilization rate under this control method is high.

Figure 3 Schematic diagram of phase shift carrier modulation

The inverters currently used generally complete the above comparison process in the CPU. When the CPU encounters interference reset or program error, the inverter will stop outputting. Using FPGA to complete the comparison process of triangle wave and sine wave will solve this problem well. The powerful computing power of CPU is used to calculate the sine wave involved in the comparison in real time, and the high-speed clock of FPGA is used to accurately generate phase-shifted triangle wave, and then the comparison output is performed in FPGA.

4 FPGA pulse generator and inertial output principle

The block diagram of the phase-shift carrier SPWM modulation implemented by FPGA is shown in Figure 4. The interface between FPGA and CPU is realized by data bus, address bus and control bus. After the CPU is powered on, the control register of FPGA is initialized first, and the output cycle of SPWM, the initial phase and amplitude of each triangular wave are set. The address generator generates the RAM read address according to the value of the cycle register, and the output data enters the cache. An interrupt is given to the CPU at the valley of each triangular wave to notify the CPU to update the data, and the data is read from the RAM at the peak of each triangular wave and enters the cache. Every time the CPU updates the data, it also updates the address register to indicate the address length of the current output data. This address length determines the frequency of the inverter output. The multi-channel comparator compares the cached data with the corresponding triangular wave in real time to generate a SPWM waveform. The optical fiber signal combiner encodes the required signals of each power unit, namely the left arm signal, the right arm signal, the locking signal, and the bypass signal into a serial signal and sends it to the optical interface.

Figure 4 FPGA realizes the structure of inverter inertia output

A watchdog (controller status detector) is implemented inside the FPGA to monitor the CPU. When the CPU is working normally, it must give the FPGA a dog feeding signal within every ms. When the detector does not detect the change of this signal within 2ms, it gives a signal to the address generator. The address generator generates an address based on the current address register to read data from the dual-port RAM, so that the phase and frequency of the inverter output can continue when the CPU crashes, that is, it has an inertial output function. When the FPGA implements inertial output, the status register saves the current output frequency value and fault flag for reading after the CPU is reset.

5 Verilog design and simulation

According to the structure diagram of Figure 4, Verilog language is used for design, and Lattice's XP3 series FPGA is selected for design. Unlike traditional SRAM-based FPGAs, Lattice Exp3 devices do not require external boot memory, so they can provide a single-chip solution, thereby reducing the circuit board area and simplifying the system manufacturing process. Taking the control state detector as an example, when the FPGA detects that the CPU's dog feeding signal has not changed within a period of time, it gives a CPU abnormal signal and changes the output strategy of the address controller. Its simulation graph is shown in Figure 5.

Figure 5 CPU status detector simulation timing diagram

6 Experimental Results

The 6kv inverter prototype developed based on the inertial output theory described in this article can manually reset the main CPU during operation, and the output voltage waveform can be consistent with the frequency and amplitude before the reset. After the main CPU is reset, the inverter output is maintained continuously according to the pre-reset data stored in the FPGA. The above experiment verifies the inertial output theory when the inverter main CPU crashes and is reset.

7 Conclusion

This paper discusses in detail the application of inertial output technology in the design of cascaded multi-level inverters. The feasibility of this technology is verified through simulation and actual prototype development. The use of this technology can greatly improve the stability and reliability of inverter output. Although the application of inertial output technology in high-voltage inverters is currently limited to prototypes, with the gradual recognition of the industry and the verification of actual operation, inertial output technology will surely become an important technical indicator for testing the next generation of inverters.