Several of the world's largest major automotive chip suppliers, Bosch, Infineon, Nordic, NXP and Qualcomm have joined forces to "invest in a company aimed at promoting global RISC-V adoption by driving next-generation hardware development." What do these companies’ actions mean? And what does this mean for the future of Arm?
RISC-V has achieved a major breakthrough as the electronics industry's largest automotive chip suppliers announced a joint venture focusing on open standard instruction set architectures.
Infineon, Nordic, NXP, Bosch and Qualcomm said the joint venture, based in Germany, will be shared equally between them and serve as a "single source for enabling RISC-V-based compliant products, providing reference architectures and helping to establish industry standards."
The company will initially focus on in-vehicle applications, while apparently leaving room for further expansion into other product areas, including mobile and IoT. However, the impact of this announcement is likely to affect the car manufacturers and Tier 1 first.
The formation of the joint venture shows that most of the key players in the automotive chip market are fully committed to RISC-V.
Considering that important players in the automotive chip industry are collaborating to formulate "industry standards" for RISC-V, their intention seems to be to launch "compatible" chip solutions for car manufacturers, a move that may relieve pressure on the automotive chip supply chain.
The joint venture sets the direction for the future of the automotive industry. Chip suppliers have certainly received incentives or clear green lights from automakers to pursue RISC-V, reduce costs, develop specific instruction sets for the automotive space, and seek to control their own destiny.
The goal of the joint venture is to "accelerate the commercialization of future products based on the open source RISC-V architecture ," but it is unclear whether the plan will include MCUs , MPUs, or even high-end CPUs equipped with a large number of RISC-V cores , which may evolve is a licensable chiplet.
As of Friday, none of the five partners had come forward to explain why they chose RISC-V over Arm.
Calista Redmond, CEO of RISC-V International, said briefly of the joint venture on Thursday that it not only "validates the work of RISC-V's global open source community, but also demonstrates 'shared industry interest and the collective investment of customers'" What can be done.”
Redmond understands that the new joint venture is a commercial entity and that its output (the joint venture's products) will be "partly proprietary" (the joint venture will own some IP), while other parts will be open sourced to the global community.
For a long time, chip companies have been dissatisfied with Arm to a certain extent. Issues include licensing fees, Arm's business style, and more. Renegades also long for greater freedom in charting their future.
However, the bottom line is that behind any industry move there is always big customer demand and business needs driving it. Redmond explained that Imagination and MIPS are the latest companies to switch to the RISC-V camp due to growing customer demand.
Other unanswered questions raised by the five companies’ move include the direction of the five companies’ own internal RISC-V development projects. It is unclear whether these plans will be folded into the new joint venture.
Another question is, why did they choose to develop their own RISC-V core? If five heavyweights are so desperate to adopt RISC-V quickly, why don't they just source RISC directly from experienced companies like Andes or SiFive -
What about the authorization of V kernel?
Most likely, the automakers hope to secure a second source in the long term while also hoping to tailor RISC-V's open instruction set architecture to their future chip needs.
The key to understanding the significance of this announcement lies in the collective investment and actions taken by major automotive chip suppliers. This is a big blow to the design, roadmap and Arm’s future business in the automotive field.
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