LVDS interface standard

LVDS interface is a common interface standard for LCD Panel. Taking 8-bit Panel as an example, it includes 5 groups of transmission lines, 4 of which are data lines, representing Tx0+/Tx0-... Tx3+/Tx3-. There is also a group of clock signals, representing TxC+/TxC-. Correspondingly, there are 5 groups of receiving lines on one end of the panel. If it is a 6-bit Panel, there are only 3 groups of data lines and one group of clock lines.

LVDS interface, also known as RS-644 bus interface, is a data transmission and interface technology that only appeared in the 1990s. LVDS is a low voltage differential signal. The core of this technology is to use extremely low voltage swing to transmit data at high speed differentially. It can realize point-to-point or point-to-multipoint connection. It has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation. Its transmission medium can be copper PCB connection or balanced cable. LVDS has been more and more widely used in systems with high requirements for signal integrity, low jitter and common mode characteristics. At present, there are two popular LVDS technical specifications: one is the ANSI/TIA/EIA-644 standard of TIA/EIA (Telecommunications Industry Alliance/Electronic Industry Alliance), and the other is the IEEE 1596.3 standard.

In November 1995, the ANSI/TIA/EIA-644 standard was launched by National Semiconductor Corporation of the United States. In March 1996, IEEE announced the IEEE 1596.3 standard. These two standards focus on the specifications of the electrical characteristics, interconnection and line termination of the LVDS interface, but do not specify the production process, transmission medium and power supply voltage. LVDS can be implemented using CMOS, GaAs or other technologies, and its power supply voltage can range from +5V to +3.3V, or even lower; its transmission medium can be PCB wiring or a special cable. The standard recommends a maximum data transmission rate of 655Mbps, and theoretically, on a lossless transmission line, the maximum transmission rate of LVDS can reach 1.923Gbps.

---- The OpenLDI standard has been widely used in laptops, and the connection interface between the LCD display and the motherboard of most laptops adopts the OpenLDI standard. The basis of the OpenLDI interface standard is the Low Voltage Differential Signaling (LVDS) interface, which has the characteristics of high efficiency, low power consumption, high speed, low cost, low clutter interference, and support for higher resolution. The LVDS interface is widely used in telecommunications, communications, consumer electronics, automobiles, and medical instruments, and has been supported by companies such as AMP, 3M, Samsung, Sharp, and Silicon Graphics. In order to penetrate into the desktop field, NS has launched new chipsets DS90C387 and DS90CF388 that support the OpenLDI standard specifically for LCD monitors. The new chipsets support resolutions from VGA (640×480) to QXGA (2048×1536).

---- Although the DVI standard is not as famous as the OpenLDI standard, and its application is not as common as the OpenLDI standard. However, due to the participation of large companies such as Intel, IBM, and HP, the application prospects of DVI are generally optimistic. Some digital CRT monitors, LCD monitors, and data projectors have adopted digital display interfaces that comply with the DVI standard.

---- At present, most computers are connected to external display devices through analog VGA interfaces. The display image information generated digitally inside the computer is converted into R, G, and B primary color signals and line and field synchronization signals by the D/A (digital/analog) converter in the graphics card, and the signals are transmitted to the display device through cables. For analog display devices, such as analog CRT monitors, the signal is directly sent to the corresponding processing circuit to drive and control the cathode ray tube to generate images. For digital display devices such as LCD and DLP, the display device needs to be equipped with a corresponding A/D (analog/digital) converter to convert the analog signal into a digital signal. After the D/A and A/D conversions, some image details are inevitably lost.

---- The DVI standard was officially launched by DDWG in April 1994. It is based on the PanalLink interface technology of Silicon Image. The PanalLink interface technology uses the Transition Minimized Differential Signaling (S) as the basic electrical connection. As shown in the attached figure, the image information generated in the computer is transmitted to the display processing unit (graphics card), processed and encoded into a data signal. The data signal contains some pixel information, synchronization information and some control information. The information is output through three channels. At the same time, there is a channel for transmitting the clock signal that synchronizes the sending and receiving ends. The data in each channel is transmitted in the form of differential signals, so each channel requires two transmission lines. Due to the use of differential signal transmission, the voltage difference signal is recognized in data transmission and reception, so the length of the transmission cable has little effect on the signal, and long-distance data transmission can be achieved. The received data is decoded at the receiving end, and the image information is processed and generated for display by the digital display device. The DVI standard strictly defines and regulates the physical mode, electrical indicators, clock mode, encoding mode, transmission mode, data format, etc. of the interface. For digital display devices, since there is no D/A and A/D conversion process, the loss of image details is avoided, thereby ensuring the complete reproduction of computer-generated images. A hot plug monitoring signal is also added to the DVI interface standard, thus truly realizing plug and play. The DVI standard received an immediate response as soon as it was launched. Not only have various graphics chip manufacturers launched a series of chipsets that support the DVI standard, but companies such as ViewSonic and Samsung have also launched digital CRT displays and LCD displays that use the DVI standard interface. We have also seen the DVI standard interface in some recently launched LCD and DLP data projectors. With the advent of the digital age, it is just around the corner for the DVI standard interface to replace the VGA interface and become the de facto standard interface for display devices. 1 Introduction to LVDS LVDS (Low Voltage Differential Signaling) is a low-swing differential signaling technology that enables signals to be transmitted at a rate of several hundred Mbps on differential PCB line pairs or balanced cables. Its low voltage and low current drive output achieve low noise and low power consumption. For decades, the use of 5V power supply has simplified the interface between logic circuits of different technologies and manufacturers. However, with the development of integrated circuits and the demand for higher data rates, low-voltage power supply has become an urgent need. Reducing the supply voltage not only reduces the power consumption of high-density integrated circuits, but also reduces the heat dissipation inside the chip, which helps to improve the integration. An excellent example of reducing the supply voltage and logic voltage swing is low-voltage differential signaling (LVDS). The LVDS physical interface uses a 1.2V bias to provide a 400mV swing signal (the reason for using differential signals is that noise is coupled on a pair of differential lines in a common mode and subtracted in the receiver to eliminate the noise). LVDS drivers and receivers do not rely on a specific supply voltage, so it is easy to migrate to low-voltage power supply systems without changing performance. In comparison, ECL and PECL technologies rely on the supply voltage. ECL requires a negative supply voltage, while PECL is based on the voltage value (Vcc) on the reference positive supply voltage bus. GLVDS is a new technology in development whose standards have not yet been determined. It can provide a 250mV signal swing using a 500mV supply voltage. The differential voltage swings of different low-voltage logic signals are shown in Figure 1.









LVDS is defined in two standards. IEEE P1596.3 (approved in March 1996), mainly for SCI (Scalable Coherent Interface), defines the electrical characteristics of LVDS and also defines the encoding of packet switching in the SCI protocol; ANSI/EIA/EIA-644 (approved in November 1995), mainly defines the electrical characteristics of LVDS and recommends a maximum rate of 655Mbps and a theoretical limit rate of 1.823Gbps on a distortion-free medium. Both standards specify characteristics that are independent of the physical medium, which means that as long as the medium sends a signal to the receiver within the specified noise margin and skew tolerance range, the interface can work properly. LVDS has many advantages: ① easy terminal adaptation; ② low power consumption; ③ fail-safe characteristics to ensure reliability; ④ low cost; ⑤ high-speed transmission. These characteristics have made LVDS widely used in computers, communication equipment, consumer electronics, etc.
Figure 2 shows a typical LVDS interface, which is a simplex mode. Half-duplex and multi-point configuration modes can also be used when necessary, but they are generally applicable when the noise is small and the distance is short. Each point-to-point differential pair consists of a driver, an interconnector, and a receiver. The driver and receiver mainly complete the conversion between TTL signals and LVDS signals. The interconnector includes cables, differential wire pairs on PCBs, and matching resistors. The LVDS driver consists of a current source that drives the differential line pair (usually 3.5mA). The LVDS receiver has a high input impedance, so most of the current output by the driver flows through the 100Ω matching resistor and generates a voltage of about 350mA at the input of the receiver. When the driver flips, it changes the direction of the current flowing through the resistor, thus generating valid logic "1" and logic "0" states. Low swing drive signals achieve high-speed operation and reduce power consumption. Differential signals provide low voltage swings with appropriate noise margins and greatly reduced power consumption. The significant reduction in power allows multiple interface drivers and receivers to be integrated on a single integrated circuit. This improves the efficiency of PCB boards and reduces costs. Regardless of whether the LVDS transmission medium used is a PCB line pair or a cable, measures must be taken to prevent the signal from being reflected at the end of the medium and to reduce electromagnetic interference. LVDS requires the use of a terminal resistor (100±20Ω) that matches the medium. This resistor terminates the circulating signal and should be placed as close to the receiver input as possible. The LVDS driver can drive the twisted pair at a speed of more than 155.5Mbps and a distance of more than 10m. The actual limitations on speed are: ① the speed of the TTL data sent to the driver; ② the bandwidth performance of the medium. Usually, a multiplexer is used on the driver side and a demultiplexer is used on the receiver side to achieve multiplexing conversion of multiple TTL channels and one LVDS channel to increase the signal rate and reduce power consumption. And reduce the number of transmission media and interfaces, and reduce the complexity of the equipment. The LVDS receiver can withstand at least ±1V ground voltage changes between the driver and the receiver. Since the typical bias voltage of the LVDS driver is +1.2V, the sum of the ground voltage change, the driver bias voltage, and the slightly coupled noise is a common-mode voltage at the receiver input relative to the receiver ground. The common mode range is: +0.2V～+2.2V. The recommended input voltage range of the receiver is: 0V～+2.4V. 2. Design of LVDS system The design of LVDS system requires the designer to have experience in ultra-high-speed single board design and understand the theory of differential signal. Designing a high-speed differential board is not very difficult. The following will briefly introduce the various points to pay attention to. 2.1 PCB board ? (A) Use at least 4 layers of PCB board (from top to bottom): LVDS signal layer, ground layer, power layer, TTL signal layer; (B) Isolate TTL signals and LVDS signals from each other, otherwise TTL may couple to LVDS lines. It is best to place TTL and LVDS signals on different layers isolated by power/ground layers; (C) Make the LVDS driver and receiver as close to the LVDS end of the connector as possible; (D) Use distributed multiple capacitors to bypass LVDS devices, and place surface mount capacitors close to power/ground layer pins; (E) Thick lines should be used for power and ground layers, and 50Ω wiring rules should not be used; (F) Keep the return path of the PCB ground layer wide and short; (G) A cable using a ground return copper wire should be used to connect the ground layers of the two systems; (H) Use multiple vias (at least two) to connect to the power layer (line) and ground layer (line). Surface mount capacitors can be directly soldered to the via pads to reduce wire ends. 2.2 On-board conductors (A) Microwave transmission lines (microstrip) and striplines have good performance; (B) Advantages of microwave transmission lines: generally have higher differential impedance and do not require additional vias; (C) Striplines provide better shielding between signals. 2.3 Differential Lines (A) Use controlled impedance lines that match the differential impedance and terminal resistance of the transmission medium, and make the differential line pairs as close to each other as possible (less than 10mm) immediately after leaving the integrated chip, which can reduce reflections and ensure that the noise coupled is common mode noise; (B) Match the lengths of the differential line pairs to reduce signal distortion and prevent electromagnetic radiation caused by phase differences between signals; (C) Do not rely solely on the automatic routing function, but carefully modify it to achieve differential impedance matching and achieve differential line isolation; (D) Minimize vias and other factors that may cause line discontinuity; (E) Avoid 90° routing that will cause resistance discontinuity, and use arcs or 45° fold lines instead; (F) Within a differential line pair, the distance between the two lines should be as short as possible to maintain the common mode rejection capability of the receiver. On the printed board, the distance between the two differential lines should be kept as consistent as possible to avoid differential impedance discontinuity. 2.4 Termination (A) Use terminal resistors to achieve maximum matching of differential transmission lines. The resistance is generally between 90 and 130Ω. The system also needs this terminal resistor to generate a normal differential voltage. (B) It is best to use a surface mount resistor with an accuracy of 1 to 2% to bridge the differential line. If necessary, two resistors with a resistance of 50Ω each can be used and connected to ground through a capacitor in the middle to filter out common-mode noise. 2.5 Unused pins All unused LVDS receiver input pins are left floating, all unused LVDS and TTL output pins are left floating, and unused TTL send/driver input and control/enable pins are connected to power or ground. 2.6 Media (cable and connector) selection (A) Use controlled impedance media with a differential impedance of approximately 100Ω, which will not introduce large impedance discontinuities; (B) Balanced cables (such as twisted pairs) are usually better than unbalanced cables in terms of reducing noise and improving signal quality; (C) When the cable length is less than 0.5m, most cables can work effectively. When the distance is between 0.5m and 10m, CAT 3 (Categiory 3) twisted pair cables work well, are cheap and easy to buy. When the distance is greater than 10m and high speed is required, it is recommended to use CAT 5 twisted pair cables.


































2.7 Designing for reliability in a noisy environment
The LVDS receiver provides a reliability circuit internally to protect the output when the receiver input is floating, the receiver input is short-circuited, and the receiver input is matched. However, it does not provide reliability guarantees in a noisy environment when the driver is tri-stated or the cable on the receiver is not connected to the driver. In this case, the cable becomes a floating antenna. If the noise induced by the cable exceeds the tolerance of the LVDS internal reliability circuit, the receiver will switch or oscillate. If this happens, it is recommended to use a balanced or shielded cable. In addition, external resistors can be added to improve the noise tolerance, as shown in Figure 3. In the figure, R1 and R3 are optional external resistors used to improve the noise tolerance, and R2≈100Ω. Of course, if an LVDS transceiver embedded in the chip is used, since there is generally a mechanism to control whether the transceiver is working, this suspension will not affect the system. 3 Application Examples LVDS technology is currently widely used in high-speed systems. This article gives a simple example to see the specific connection method. In the DSLAM (Digital Subscriber Line Access Module) solution of Canada PMC Company, LVDS technology is used to achieve point-to-point single-board interconnection. The system structure has very good scalability, and a high degree of integration on the line card is achieved. It can fully meet the requirements of large amounts of business data and control flow communication brought about by business dispersion and control concentration. Figure 4 describes the connection between the line cards and the line cards and the backplane of the system. All of them use simplex mode, so two pairs of lines are required to achieve two-way communication. The figure shows three different connection methods, from top to bottom: there is a corresponding connection chip; terminal matching is achieved when crossing racks; terminal matching is achieved when the frame is on the same layer. Connecting a transformer in series at the receiving end can reduce interference and avoid the influence of the large ground potential difference between the LVDS driver and the receiver. LVDS interface definition .