How to use the MAX2902 with an external frequency synthesizer

The MAX2900-MAX2904 are monolithic 200mW transmitters designed for the 868MHz/915MHz bands. Each chip integrates a baseband pseudo-random (PN) sequence lowpass filter, transmit modulator, power amplifier, and RF VCO. The MAX2900, MAX2901, and MAX2903 also include a complete frequency synthesizer, allowing these devices to be used as a complete RF transmitter solution. The MAX2902 and MAX2904 are designed to be used in conjunction with an external frequency synthesizer to provide maximum flexibility in frequency planning and channel setting.

When selecting a frequency synthesizer chip, the first step is to decide whether to use an integer-N or fractional-N frequency synthesizer. A well-designed Σ-Δ fractional-N frequency synthesizer can provide excellent performance in terms of phase noise, PLL lock time, and phase noise suppression. Although the cost of fractional-N frequency synthesizers continues to decrease, integer-N frequency synthesizer chips still provide a more affordable solution. Understanding how performance parameters are traded off will help make the right decision in which frequency synthesizer to use.

Phase detection frequency

One major difference between using the MAX2902 with an external fractional-N synthesizer versus an integer-N synthesizer is that a higher phase-detection frequency (F _COMP ) can be used while maintaining the same or, in many applications, smaller frequency resolution or step size (F _STEP ). In integer-N synthesizers, the step frequency is the same as the phase-detection frequency. In fractional-N synthesizers, however, the step frequency is related to the phase-detection frequency by the relationship, F _STEP = F _COMP /2 ^BITS, where BITS is the fractional number of bits in the synthesizer.

A high phase-detection frequency can significantly reduce the in-band phase noise of the local oscillator (LO) signal. Phase noise is proportional to the value of the primary divider (N) in the synthesizer. Increasing the phase-detection frequency requires a smaller value of N for the same RF frequency, thereby reducing the noise contribution of the divider. The reduction in phase noise can be calculated as follows:

Loop Bandwidth

As the detector frequency of the synthesizer increases, a wider loop bandwidth can be used without degrading the detection noise rejection. As the detection frequency increases, the detection noise is pushed farther away, allowing the 3dB point of the loop filter to be moved farther away while still maintaining adequate rejection of the reference spurs.

The advantage of increasing the loop bandwidth is that the lock time is faster. The lock time is inversely proportional to the loop filter cutoff frequency, so increasing the loop bandwidth can reduce the lock time of the PLL. In many applications, lock time is a critical parameter, and fractional-N synthesizers with wide loop bandwidths are very important.

The disadvantage of increasing the loop bandwidth is that the detector noise is integrated over a wider bandwidth. The phase noise is constant within the loop filter cutoff frequency and begins to roll off outside of it. Therefore, as the loop filter corner frequency is moved farther away, the integrated phase error of the LO signal will also increase according to the formula, ΔIntegrated Noise = 10 x log(F ₂ /F ₁ ) where F1 and F2 are the narrow and wide loop bandwidths, respectively.

Note the coupling

The MAX2902 has an on-chip power amplifier capable of outputting up to +23.5dBm (typ). This high power value can easily cause the modulated RF output signal to couple into the VCO routing between the MAX2902 and the frequency synthesizer chip. Careful consideration of routing and grounding will help reduce coupling, but it is usually difficult to completely eliminate the effects of coupling due to layout space constraints. Interfering signals on the VCO line will cause the LO phase noise performance of the MAX2902 to deteriorate. The wider the loop bandwidth, the less impact the RF coupling has on the circuit because the closed loop will attenuate the coupled noise. However, as mentioned earlier, a wide loop bandwidth will increase the integrated phase error of the system.

Application Examples

Two examples are provided in this note. The first example uses an integer-N synthesizer architecture, while the second uses a fractional-N synthesizer architecture. Both integer and fractional modes of the same synthesizer chip are used to illustrate the typical performance of the MAX2902 in closed loop. The setup parameters for both configurations are listed below along with the phase noise characteristics graph. Both configurations provide viable real-world solutions based on the overall synthesizer requirements.

The fractional-N synthesizer used has a 4-bit fractional bit count, which is able to provide fractional quantities modulo 16. This allows the phase-detection frequency to be 8 times greater than the integer version while providing a step frequency spacing of less than 50%. This difference would be greater if a fractional synthesizer with a larger modulus was used.

From the phase noise graph, it can be seen that the difference in in-band phase noise is (-73.00 - -82.83) = 9.83dB. This value is very close to the theoretical difference of 10 * log (5856/732) = 9.03dB based on the calculation formula for different N values. Therefore, the fractional synthesizer improves the in-band phase noise. However, when calculating the integrated phase error, the integral phase error values ​​obtained by the integer and fractional methods converge to -29dBc and -30dBc, respectively. In the example using a fractional frequency synthesizer, the wide loop bandwidth improves the PLL lock time by about 5 times, although it loses the initial phase noise advantage.

in conclusion

The MAX2902 is a highly integrated transmitter chip that can be combined with integer-N or fractional-N frequency synthesizers to build a complete transmitter solution. When choosing which frequency synthesizer to use with the MAX2902, it is important to first understand and evaluate the key performance indicators and their trade-offs. Phase noise, lock time, channel spacing, and cost will also vary depending on the frequency synthesizer solution.