Using a differential amplifier to drive an analog-to-digital converter

High-speed differential amplifiers provide greater flexibility in signal chain designs that include high-speed analog-to-digital converters (ADCs). Differential op amps can provide signal conditioning functions including gain, impedance transformation and single-ended to differential conversion.

ADCs are generally fixed-gain devices that perform best when the input signal amplitude is smaller than the full-scale input range. Distortion is introduced when quantizing a signal with an amplitude less than one LSB. Distortion will also be introduced to signals whose amplitude exceeds full scale. Many ADCs can be damaged by slight overdrive. The CLC5526 is a variable gain differential amplifier that can provide signal gain or attenuation when driving a high-speed ADC. It can obtain an additional 42dB of dynamic range under microcontroller control. The LMH6550 is ideal for applications requiring low distortion, fixed gain and DC coupling. Differential amplifiers like the LMH6550 can select precise common-mode operating points. Both the LMH6550 and CLC5526 provide the low impedance and highly flexible driving capabilities required to drive CMOS analog-to-digital converters like the ADC12DL065.

When selecting an op amp to drive an ADC, it is most important to first define the system requirements. Key parameters to consider include bandwidth, distortion, balance error and settling time. For broadband signals, distortion is often the deciding factor. On the other hand, for narrowband signals, bandwidth will determine the choice since distortion can be eliminated by DSP. Narrowband signals are characterized by intermodulation and harmonic distortion that fall outside the band, whereas for wideband signals these will fall within the band. Next we will discuss in more detail how to select a device based on signal and ADC characteristics.

First, let’s review the basics of ADC. As a mixed-signal device, the ADC includes analog and digital circuits. The digital portion of the ADC operates at a clock sampling frequency, which is usually fixed in a particular application. The sampling frequency determines many key parameters, which will be discussed in detail later. When quantizing a signal, the ADC is bound by Nyquist theory. Nyquist theory states that the sampling frequency must be at least twice the highest frequency of the signal. Otherwise you will end up with the generation of "aliased" signals. To the ADC, the aliased signal does not represent its true frequency. Aliased signals may be undesirable and must be considered in system design. Figure 1 demonstrates the aliasing phenomenon through sampling results in the frequency domain. Depending on the application, the aliased signal frequency may be higher or lower than the desired signal. Analog filtering and selecting appropriate sampling and signal frequencies can eliminate distortion due to aliasing.

Figure 1 Nyquist sampling. It shows multiple harmonic components falling back into the Nyquist band. LMH6550 drives ADC12L080, sampling frequency = 64MHz, signal frequency = 9.8MHz.

Nyquist Sampling

The classic and perhaps most familiar analog-to-digital converter application is the Nyquist application. In this example, the signal includes all frequency components from DC to half the ADC sampling frequency. Nyquist theory stipulates that the signal must be quantized by a sampling frequency that is at least twice greater than the highest frequency of the signal (it does not apply to the carrier of the modulated signal, but only refers to the part that actually contains information in the signal). Taking the digitized telephone voice signal as an example, the required signal The frequency is from 300Hz to 3kHz, so the sampling frequency of the ADC must be at least 6KHz. In the United States, telephones use a sampling rate of 8KHz and a resolution of 8 bits when converting to digital signals. Although Nyquist sampling is the minimum requirement to ensure correct operation of the ADC, anti-aliasing filters are still very important to ensure system performance.

Similarly, Nyquist sampling also places strict requirements on the driver amplifier. The amplifier has a bandwidth of at least 0.1dB at 1/2 the sampling frequency. At 1/2 the sampling frequency, the amplifier and ADC must have similar distortion and noise characteristics. If the amplifier is used as an active filter, the -3dB bandwidth should be close to twice the sampling frequency. In general for Nyquist sampling, the amplifier and ADC should have similar performance parameters at half the sampling frequency and below. A fixed-gain amplifier such as the LMH6550 is ideal for DC-coupled signals. For broadband signals below 50MHz, buffering is required, which is very suitable when small fixed gain and high signal purity are required. LMH6550 can also replace the transformer to complete the conversion from single-ended to differential signals.

Oversampling

The rapidly developing ADC technology provides signal chain designers with more choices. Today's ADCs can operate with clocks that far exceed the signal bandwidth required. This method is called oversampling.

A key benefit of oversampling is the subsequent digital filtering process. Digital processing can be performed from the upper limit frequency of the signal to one-half the sampling frequency. Digital filters are easy to adjust and have high accuracy. And it is easy to integrate with other digital processing, such as downconversion and demodulation. Digital filters can eliminate almost all ADC out-of-band noise. The signal-to-noise ratio improved by digital filters is also known as processing gain. Processing gain is usually measured in dB, which is the ratio of the signal-to-noise ratio after filtering to the signal-to-noise ratio before filtering. But DSP cannot eliminate noise within the signal bandwidth. Careful selection of gain settings and feedback resistors can help limit the noise introduced by the amplifier to a minimum.

Undersampling

An ADC operating in an undersampling mode is similar to an analog mixer. Nonlinear mixing is an old technology and is popular in heterodyne and superheterodyne receivers.

Undersampling is often used in oversampling structures, where the signal bandwidth is much lower than one-half the sampling frequency. Careful selection of the appropriate IF frequency and sampling frequency allows the DSP after the ADC to eliminate most of the noise introduced by the analog signal chain and the distortion generated by the ADC. This is the same benefit described in Oversampling. This is important because anti-aliasing filters at higher carrier frequencies require a higher Q than filters at one-half the sampling frequency and signal bandwidth. Without oversampling, undersampling is also impractical.

Figure 2 is the undersampling conversion result of LMH6550 driving ADC12L080, which can improve the dynamic range without spurious frequencies within a narrow width. The SFDR of the demo system was only 32dB. However, it is clearly found that the SFDR is 65dB in the bandwidth from 10MHz to 28MHz. If the bandwidth is narrower, the SFDR can be increased to more than 80dB. In the GSM system only a bandwidth of 200kHz is required. A simple two-stage LC filter between the amplifier and ADC can filter out the noise generated by H2, H3 and the driver amplifier. Digital signal processing can eliminate most distortion. The operational amplifier characteristics and key parameters are shown in Table 1.

Figure 2 LMH6550 driver? ADC12L080 undersampling conversion result. The signal frequency is 146MHz. The sampling frequency is 64MHz. Fs/2*4=128MHz 146-128=18MHz

input matching

The load of the analog-to-digital converter is always difficult to design. Typically there is a high input impedance and a large and variable capacitive reactance. At the same time, switched capacitors or sample-and-hold circuits can generate current spikes. For these reasons, the ADC input is difficult to match and an amplifier must be used. The differential amplifier's output stage eliminates current spikes while providing a low-impedance source for accurate sampling. Figure 3 shows a typical circuit for driving an ADC. Two 56Ω resistors are used to isolate the capacitive load of the ADC from the amplifier to ensure stability. At the same time, these resistors are also part of the low-pass filter, used to provide anti-aliasing filtering and noise attenuation functions. The two 39pF capacitors are used to eliminate current spikes caused by the ADC's internal switching circuitry and are also key components of the low-pass filter for the ADC input. In the circuit of Figure 3, the cutoff frequency of the filter is 1/(2*p*56W*(39pF+14pF))=53MHz (slightly lower than the sampling frequency). Note that the input capacitance of the ADC must be considered when calculating the filter frequency response. If it is a differential input, the effective input capacitance value must be doubled. Also, as shown in Figure 3, the input capacitance of many ADCs is part of the ADC conversion process (sample and hold circuit).

Figure 3 Driving the ADC. LMH6550 drives ADC12LO66.

Like all high-speed circuits, circuit board layout is critical. The amplifier and ADC should be as close as possible. Both amplifiers and ADCs require filtering components to be placed closely together. Amplifiers require as low a parasitic load as possible on the output conductors, and ADCs are also sensitive to high-frequency noise that may couple on the input conductors. In addition, the digital output of the ADC should be well isolated from the inputs of the ADC and amplifier. Amplifier and ADC input pins should not be placed on power or ground planes. Power supply bypass capacitors should meet low ESR and be placed within 2mm from the relevant pins. It's also a good idea to use multiple vias if necessary.

Common-mode feedback

The main advantage of a common-mode feedback circuit is that the differential amplifier can accurately set the output common-mode voltage value. For most ADCs, the common-mode voltage must be set to a specific value to obtain full dynamic range. Theoretically, a differential amplifier will only amplify the differential signal, and the common mode part of the output can be set independently without affecting the gain and differential output signal. Amplifiers like the LMH6550 have a common-mode voltage output buffer with a high-impedance input. This allows the amplifier to use the reference voltage output by most ADCs without imposing a large loading effect on the ADC's reference voltage generation circuitry.

Another advantage of common-mode feedback circuits is the use of amplifiers to produce fully differential signals from a single-ended source. It also balances the two differential output stages at an ideal common-mode voltage point.

Figure 4 Single-Supply Operation and DC Operating Point

It is important to note that the common-mode feedback circuit looks similar to a unity-gain buffer, acting as a buffer between the input pin and the output common-mode voltage. The equation Vocm=(V+out+V-out)/2 shows that the two outputs have the same amplitude and opposite phase relative to the output common-mode voltage. Figure 4 shows a typical structure for single-supply operation and gives the formula for calculating the effect of a common-mode feedback network. In this example, Vcm is the input to the common-mode feedback buffer. Vocm is the output common-mode voltage, or the output of the common-mode feedback buffer. When using a differential amplifier powered by a single-ended supply, the input common-mode voltage operating point is no longer the primary limiting factor in system design. Single-ended power supply will limit the gain and output common-mode voltage setting range.