What does LVDS mean?

What does LVDS mean?

Abstract: Compared with ECL, PECL and CML standards, the ANSI EIA/TAI-644 low voltage differential signaling (LVDS) standard has advantages such as low power consumption and low noise radiation. This article mainly discusses the characteristics of LVDS and its possible applications.

In recent years, with the increase in clock frequencies of microprocessors, DSPs, and digital ASICs, the data rate and bus throughput of backplane signals in some emerging fields have also been steadily increasing. The increase in speed has made the weaknesses of TTL-based single-ended signals more and more prominent, mainly manifested in: increased power consumption, jitter (causing bit errors), high-level radiation, etc. Although some reports believe that the speed can be maintained above 50MHz using this technology, due to transmission line impedance mismatch and crosstalk, as well as more difficult power supply decoupling problems, designers are forced to seek more effective solutions.

One way to increase the bandwidth of all buses and backplanes is to increase the bus width, but this approach increases the difficulty of circuit board layout and requires connectors with a large number of pins, resulting in high system cost and very bulky. When the distance exceeds a few centimeters, using serial communication is an effective solution to the above problems. High-speed communication systems, such as 3G base stations, routers, load/unload multiplexers and other equipment, can benefit greatly from serial communication.

In order to ensure low bit error rate, low crosstalk and low radiation in backplane communication, it is recommended to use low voltage differential signaling (LVDS) instead of TTL signaling.

Characteristics of LVDS, ECL, PECL, and CML

LVDS has been increasingly used in systems that require signal integrity, low jitter (jitter is defined as the deviation of the output transition time of the signal from the ideal value) and high common mode characteristics. It is one of the effective solutions for high-speed serial interfaces. Other standards include (arranged from low speed to high speed): ECL (emitter coupled logic), PECL (positive ECL), CML (current mode logic), each standard is different from each other.

ECL is a traditional high-speed logic standard, which is based on bipolar crystal differential pairs and uses a negative bias power supply. PECL is developed from the ECL standard, and the negative power supply is omitted in the PECL circuit. The new generation of ECL devices has a delay time of about 200ps and can be used in systems with frequencies greater than 3GHz.

Among the existing interface standards, CML has the highest operating speed and can be used in systems with gigabit data rates. Compared with other standards, it also has an integrated 50Ω matching resistor, which greatly simplifies the design. When each endpoint operates at a different power supply voltage, an external coupling element is required.

This article mainly discusses the characteristics of LVDS and its possible applications. Table 1 lists the characteristics of LVDS relative to ECL, PECL, and CML systems. According to the EIA/TIA-644 LVDS and IEEE 1596.3 standards, LVDS uses differential signals with a signal range of 250mV to 400mV and a DC bias of 1.2V.

Table 1. The output signal swing of ECL and PECL transmitters is higher than that of LVDS. The higher output swing and shorter transmission delay make ECL and PECL devices have higher costs and power consumption.

Differential Voltage Swing
DC Offset
Propagation Delay

Advantages of LVDS

The differential characteristic brings many advantages to LVDS: suppressing common-mode noise and not generating noise itself (assuming that the differential signal is completely synchronized and there is no distortion between the positive and negative outputs). In addition, LVDS can be implemented using CMOS technology, which is convenient for integration with other circuits.

Since LVDS is a differential signal, the peak value of the power supply current is low, and the power supply decoupling problem can be solved by adding appropriate decoupling capacitors. Generally, LVDS consumes less power than ECL and CML. Of course, this depends to some extent on the matching scheme used.

Applications of LVDS

LVDS is mostly used for clock distribution and point-to-multipoint signal distribution. Clock distribution is very important for digital systems where different subsystems need the same reference clock. For example, in most cases, the DSP of the base station needs to be synchronized with the RF signal processor, using a phase-locked loop (PLL) to generate the required local oscillator frequency, and the A/D conversion is locked to the central reference clock. When working with a wireless receiver, the clock must also be distributed with the lowest possible radiation to avoid affecting the small signal path.

There are different strategies for distributing high-speed signals to different units, with two extremes: one is to distribute the signal from one source/driver to all units (called a "multipoint distributor"); the other is to distribute multiple signals to one unit (called a "multipoint to single-point distributor." Figure 1 illustrates the difference between these two situations. For a multipoint distributor, the driver must be strong enough to drive all receivers and transmission media (cables, connectors, backplanes), and the bus usually needs to be matched at the final receiver. The distance between all branches and the bus must be as short as possible to avoid signal integrity problems, which is not easy to achieve with today's high-density circuit boards.


Figure 1. Multipoint signal distribution allows communication between a transmitter and multiple receivers without the need for intermediate connectors and eliminates the interference caused by connectors. The

multipoint to single-point distribution structure requires multiple drivers, which can be defined as point-to-point operation, equivalent to communication between the driver and a local terminal receiver. This structure reduces signal integrity issues, ensures that the impedance of the transmission medium is as consistent as possible, and eliminates interference caused by multiple branches.