Development of NO.7 signaling acquisition card based on PCI bus technology

At present, the NGN network is a complex network with soft switching as the core and PSTN network and VoIP network integrated together. There are multiple interfaces , multiple protocols, and multimedia coexisting. The compatibility of PSTN and VoIP equipment, the compatibility of equipment of different equipment providers in the VoIP network, the difference between network design performance and actual deployment performance, and the difference in voice quality are all serious challenges facing operators. Therefore, NGN network operators are required to test and analyze their network performance. NGN network testers can solve such problems.

This NO.7 signaling acquisition card is designed based on PCI bus technology, and its main functions are physical layer data acquisition and HDLC link control . This card mainly completes NO.7 signaling acquisition according to the protocol selection, and sends the data to the upper layer software of the NGN network tester for analysis.

The overall design and hardware implementation of the NO.7 signaling acquisition card
The NO.7 signaling acquisition card is a very important data acquisition card in the NGN network tester. The main functions completed in the NGN network tester are data acquisition and HDLC link control at the physical layer. In order to meet the requirements of large data flow during testing and convenient user use, the design of this card uses an HDLC controller (MindSpeed ​​CN8478) with standard PCI protocol specifications, a dedicated E1 framer (IDT82P2284) chip and Windows 2000 as the basic software and hardware architecture of this card. The software driver of this card is based on the PCI framework and can achieve fast and stable acquisition of NO.7 signaling. Figure 1 is a block diagram of the overall design of this card.

Figure 1 Overall design block diagram of NO.7 signaling acquisition card

According to the overall design of the NGN network tester, the NO.7 signaling acquisition card exists in the tester as a PCI slot card. The NO.7 signaling is extracted from the network through the E1 data acquisition line with a high-impedance adapter and sent to the framer chip IDT82P2284. The data is processed by IDT82P2284 and then reaches the serial port of CN8478. The HDLC frame formed in CN8478 is sent to the upper-layer software for protocol analysis and processing. This card can realize 16-channel monitoring and 4-channel simulation.

The hardware of NO.7 signaling acquisition card is mainly composed of the following units: HDLC logic layer MUSYCC (CN8478), physical layer E1 framer (IDT82P2284), CPLD logic controller, RJ45 network interface, high impedance adapter, etc. The hardware design block diagram of this acquisition card is shown in Figure 2.

Figure 2 Hardware block diagram of NO.7 signaling acquisition card

Chip Resource Introduction

1 Introduction to CN8478
CN8478 is a PCI multi-function device, which includes the following parts: a host interface Host Interface, 8 serial interfaces, an expansion bus interface (EBUS), and a boundary scan interface Boundary Scan and Test Access. Among them, the host interface is composed of four parts: device configuration register, PCI function 0 configuration space, PCI function 1 configuration space, and PCI interface. The serial port also has four components: interrupt controller, DMAC, bit-level processor BLP, receiving and sending ports. The host interface mainly provides an interface between CN8478 and PC, completes the configuration of device registers and the reading and writing of the PCI function area configuration interval. The serial port mainly completes the data transmission between the host interface and IDT82P2284, and generates interrupts as needed and notifies the PC; the EBUS interface mainly completes the expansion of peripheral devices through the built-in MPU (microprocessor unit), which is used to read and write the registers of IDT82P2284 to control it; boundary scan is not used in this system. Figure 3 is the design schematic diagram of the PCI interface of CN8478.

Figure 3 CN8478 PCI interface design schematic

2 T1/E1 transceiver framer IDT82P2284 Introduction
IDT82P2284 is a T1/E1 transceiver framer that supports four links. The data transmission rate of the transceiver interface supports 1.544Mbps of T1 or 2.048Mbps of E1. Physical linear interface Circuit Recovers the analog clock and data of "+3～-43dB" from the cable . IDT82P2284 consists of the following parts: microprocessor interface (MPU), receive/transmit linear interface unit (RLIU/TLIU), boundary scan (JTAG).

Introduction to acquisition mode
The N0.7 signaling acquisition card developed in this design can realize two modes of acquisition, namely N×64K and high-speed 2M.
In the N×64K acquisition mode, the IDT82P2284 of the PHY layer can be controlled to work in multiplexing mode, so that the four E1 links on the framer chip are combined into one and sent to a serial port of CN8478. At this time, the IDT82P2284 and serial port clock are 8.192MHz, which is provided by the dedicated clock chip on the board. In the N×64K acquisition mode, 16 channels of NO.7 signaling acquisition can be realized.

In the high-speed 2M acquisition mode, the IDT82P2284 can also be controlled. At this time, it works in non-multiplexing mode, so that each E1 link of the framer can send data to a serial port of CN8478 independently. At this time, the interface clock between the IDT82P2284 and the serial port is 2.048MHz, which is extracted by the framer on the network line. In the high-speed 2M acquisition mode, 8-channel and 16-channel NO.7 signaling acquisition can be realized simultaneously.
Driver design of NO.7 signaling acquisition card

1 Driver Function Design
The design of the N0.7 signaling acquisition card driver can be divided into two parts, corresponding to the configuration of CN8478 and the configuration of IDT82P2284 respectively.
In the configuration of CN8478, the main task of the driver is to complete the configuration of the shared body mapped in the host. The shared body is a storage space requested by the driver to the operating system, which is physically in the host's memory. Overall, the shared body can be divided into two parts. The first part is used for the register mapping of CN8478, and the second part is used for the allocation of interrupt queues, send message linked lists, receive message linked lists, send data buffers, and receive data buffers.

In the configuration of the framer IDT82P2284, its registers are mainly controlled through the microprocessor interface to realize the formation of the required frame structure message from the bit stream collected online to send to the LINK layer device.

2 Driver Implementation
This NO.7 signaling acquisition card needs to implement two drivers, corresponding to the LINK driver of CN8478 and the PHY driver of IDT82P2284. Since the PHY driver is relatively simple, this article mainly introduces the LINK driver.

This design uses the DriverWorks development tool to write the LINK driver, which is somewhat different from the driver written directly with the DDK. Here, two classes provided by DriverWorks (i.e., the Kdriver class and the KPnpDevice class) are mainly inherited to implement this driver.
Kdriver class: This class provides the basic framework structure of the device program and is responsible for distributing IRPs to the target device object. In this driver design, a derived class of the Kdriver class is inherited. The DriverEntry routine is overloaded in this derived class, and some initialization work is mainly performed in this routine. In addition, this class also contains an AddDevice routine, which is called by the PnP manager to initialize the device controlled by the driver.

KPnpDevice class: This class represents the device driver, provides the interface function between the driver and the application, undertakes the IRP distribution task, provides the interface function with the underlying device, and also provides the interface function with other system objects. It contains most of the driver routines.

3 Driver Debugging
To debug this driver, this design uses a KDebugOnlyTrace class object to output debug trace information in DriverMonitor. SoftICE is also often used to view memory values ​​to confirm the configuration information of the shared body. Figure 4 shows the debug information output using DriverMonitor.

Figure 4 Driver debugging display

Conclusion
This acquisition card has been successfully developed and put into commercial use. It is one of the most important data acquisition cards for core network testing in NGN network testers. Field tests have shown that this acquisition card can correctly and stably acquire high-traffic NO.7 signaling in NGN networks, thereby enabling NGN network testers to test and analyze NGN network protocols. At the same time, the feasibility of the NO.7 signaling acquisition card developed in this paper has also been verified.