Design of CMOS Frequency Divider Circuit

The design of clock frequency division circuit for the receiving end of high-speed serial transceiver system is discussed . Through the analysis of the working principle of twisted ring counter, a frequency division circuit based on twisted ring counter is proposed , which can realize odd and even frequency division in a selectable mode and achieve the corresponding duty cycle. The designed circuit is simulated by Cadence Spectre under SMIC 0.18um CMOS process. The results show that the circuit can complete the corresponding frequency division of 1.25GHz clock.

1 Introduction

At present, in high-speed serial data transmission systems, the transmitted data is mostly encoded into a self-synchronous data stream using the 8B/10B encoding scheme. Therefore, in order to perform 8B/10B decoding at the receiving end, the data needs to be converted from serial to parallel at 1:8/1:10; In high-speed transceiver systems, in order to achieve a higher transmission rate under a specific process, a half-rate structure is usually used, which can effectively reduce the clock frequency on the chip, so that the circuit can adapt to the processing of high-speed data streams with lower power consumption and simple structure. Therefore, in order to complete the 1:8/1:10 demultiplexing of serial input data, it is first necessary to provide a 4- or 5-frequency division clock whose duty cycle and jitter performance meet the corresponding requirements. This article discusses how to design a mode-selectable 4-frequency division and 5-frequency division circuit at the receiving end of a high-speed transceiver system. The designed circuit not only realizes the 4 or 5-frequency division of the reference clock, but also realizes different duty cycles of the divided clock.

In Section 2, the working principle of the twisted ring counter is briefly introduced, and a frequency division method similar to the twisted ring counter is proposed based on actual conditions; in Section 3, the design implementation and simulation of the CMOS frequency division circuit based on the twisted ring counter are discussed; in Section 4, the design process is briefly summarized.

Working principle of type 2 twist ring counter

The twisted ring counter, also known as the Johnson counter, is composed of a shift register plus a certain feedback network. The block diagram of the twisted ring counter composed of a shift register is shown in Figure 1. It is composed of a shift register and a closed loop of a combination feedback logic circuit. The output of the feedback circuit is connected to the serial input end of the shift register, and its input end is connected to the reverse output end of the lowest bit of the shift register, so its counting length N=2n. After n clocks, the state of the counter is exactly opposite to the initial state, and it must be twisted back to the original state after n clocks.

However, since the shift register is composed of a group of D flip-flops, it can only count the integers of the input clock, and it is impossible to complete the odd-number division of a specific duty cycle. Considering that the holding time of each level of the latch is half a clock cycle, a quasi-twisted ring counter composed of latches can be used to achieve clock division. It can be imagined that: after two levels of latches, it is delayed by 1 clock cycle, after three levels, it is delayed by 1.5 cycles, after four levels, it is delayed by 2 clock cycles, and so on. The clock division circuit needs to achieve a controllable 4- or 5-frequency division, and at the same time, the duty cycle must meet the requirements. Therefore, the output clock signal can meet the required phase relationship through the corresponding control and feedback logic.

CMOS Implementation and Simulation of 3-Divider Circuit

According to the analysis in the second part and the actual use requirements, the clock frequency division circuit shown in Figure 2 is designed. In the figure, Mode is the frequency division mode selection signal: Mode is low, completing the 4-frequency division of the input clock signals clkI and clkIN; Mode is high, and 5-frequency division is performed. The divided clock is used for subsequent data serial-to-parallel conversion. Due to different usage angles, different frequency division clocks need to be generated. The clock duty cycle used for the shift storage chain: Mode is low, that is, 1:3 when divided by 4; Mode is high, that is, 1:4 when divided by 5; the clock duty cycle used for synchronous output is 1:1.

As can be seen from Figure 2, the clock frequency division module consists of a twisted ring counter and corresponding combinational logic and feedback network.

The twisted ring counter is the core of the circuit, which consists of the latch and auxiliary logic shown in Figure 3. The circuit can complete the 4- and 5-frequency division of the input clock when the Mode signal is at different levels. Its working process can be analyzed as follows:

When the control signal Mode = '0', that is, the clock is divided by 4, the working path of the twisted ring counter is 1s → 2s → 3s → 4s → 9s → 1s. The circuit can be self-starting. Assuming that the initial state is 10101, its working process is:

At this point, a cycle has appeared. From its working process, it can be seen that the period of the divided clock is 4 times that of the input clock (8× T/2=4T), that is, divided by 4. In order to achieve the corresponding clock duty cycle requirements, combined with Figure 2 and the above analysis, it can be seen that the output clock signal:

clk_4_5 = 2s, its duty cycle = 1:1; clk_4_5_N = 2s, its duty cycle = 1:1;

clk_4_5_div_1:1= 4s, its duty cycle = 1:1; clk_4_1:3_5_1:4=3s?9s, its duty cycle = 1:3.

When the control signal Mode = '1', that is, the clock is divided by 5, the working path of the twisted ring counter is 1s → 2s → 3s → 4s → 5s → 6s → 7s → 8s → 9s → 1s. The circuit can be self-starting. Assuming the initial state is 100101010, its working process is:

At this point, a cycle has appeared. From its working process, it can be seen that the period of the divided clock is 5 times that of the input clock (10 ×T/2=5T), that is, 5 division. In order to achieve the corresponding clock duty cycle requirements, combined with Figure 2 and the above analysis, it can be seen that the output clock signal:

clk_4_5 = 2s, its duty cycle = 3:2; clk_4_5_N = 2s, its duty cycle = 2:3;

clk_4_5_div_1:1= 4s, its duty cycle = 1:1; clk_4_1:3_5_1:4=3s?9s, its duty cycle = 1:4.

For clock signals clk_4_5 and clk_4_5_N, the duty cycle should be 1:1, but the direct functional effect cannot be achieved by simply observing the circuit. Therefore, it is necessary to pass the 2s signal through a duty cycle adjustment circuit composed of a buffer chain before outputting it, so as to meet the expected requirements by adjusting the rise and fall time of the signal.

The clock frequency division circuit is simulated using Cadence's Spectre simulation tool in the SMIC 0.18um CMOS process, and the simulation waveforms are shown in Figures 4 and 5. Figure 4 shows the core circuit: the working waveform of the twisted ring counter. Figure 5 is the corresponding divided clock signal obtained after the output signals of each level of the twisted ring counter pass through the combinational logic. It can be seen from Figures 4 and 5 that the clock frequency division results are consistent with the expected functional requirements.

4 Summary

This paper analyzes the design of the clock frequency division circuit used in the receiving end of the high-speed transceiver system. By analyzing the counting principle of the twisted ring counter, a frequency division circuit based on a twisted ring counter is proposed. The circuit can realize odd and even frequency division in a selectable mode, and achieve the corresponding duty cycle through combinational logic and feedback network according to actual needs. The CMOS implementation of the circuit is given in this paper, and the simulation is carried out using Cadence's Spectre under SMIC 0.18um CMOS process. The results show that the circuit can meet the expected requirements.

Innovation of this article: Through the analysis of the principle of twisted-ring counter, a frequency division circuit based on a twisted-ring counter is proposed, which can realize odd and even frequency division in a selectable mode and achieve the corresponding duty cycle.