Design of background noise subtraction circuit based on VerilogHDL

This paper introduces a background noise subtraction circuit design based on the hardware description language VerilogHDL. Compared with the previous circuit composed of addition and subtraction counting chips, this design has the advantages of simple interface with MCU and convenient software operation.

1 Introduction

In the weak signal detection method, it is often necessary to convert the DC quantity into an AC signal after being photoelectrically modulated by LEDs for measurement, so as to reduce the background noise and improve the system signal-to-noise ratio. Satellite-borne ultraviolet remote sensing instruments also use voltage-frequency conversion and modulation and demodulation to reduce background noise and zero drift in real time, but the original unit for realizing the background noise reduction function is slightly cumbersome in terms of MCU interface and software control , and the wiring area is large. If the background noise reduction function can be designed into a dedicated integrated circuit with a universal interface and easy operation , it will have a positive significance for the upgrading of the instrument.

The hardware description language VerilogHDL provides a way to describe digital systems at a wide range of abstract levels. It has won the favor of many hardware designers with its C language style and easy-to-master features. After the hardware functions are realized through software programming, they are downloaded to FPGA or CPLD large-scale programmable logic devices, which can integrate circuit board-level products into chip-level products.

Therefore, this paper uses VerilogHDL for programming and adopts a top-down design method. After simulation verification and synthesis, a background noise circuit with a universal interface and easy-to-operate software is obtained, which makes up for the shortcomings of the original unit and achieves better results.

2 Background noise subtraction circuit principle

The electronic control part of the ultraviolet spectrum remote sensing instrument consists of a chopper, a precision high-voltage power supply , a photomultiplier tube, a single-chip control unit, a synchronous accumulative demodulation unit, a pre-low noise amplifier, and a voltage-frequency conversion. The chopper chops the spatial radiation light into alternating "signal + background" and "background" light signals, so that the signal output by the photomultiplier tube is shown in Figure 1. After the modulated signal is amplified, it is converted into a frequency signal after voltage-frequency conversion and processed by the synchronous accumulator unit. The synchronous accumulative demodulation unit uses four 4-bit binary add-subtract counters SN54HC193 with their carry bits connected to form a 16-bit add-subtract counter, and is equipped with a logic gate circuit. The background noise subtraction function is realized by relying on the 16-bit add-subtract counter controlled by the timing, adding counts in the light-transmitting state and subtracting counts in the light-shielding state, and multi-cycle counting.

Figure 1 The signal output by the photomultiplier tube after being modulated by the chopper

The principle of background noise subtraction is simple, but the timing control is more complicated. Due to many considerations such as the wiring area and the difficulty of having too many hardware chips, the original circuit uses two software interrupt settings to implement the counting cycle and start-stop control. As shown in Figure 2, the first interrupt is from the National Natural Science Foundation of China project approval number: 60538020 to start counting. It enters when the first rising edge of the chopper signal is queried. After setting the counting cycle, the MCU chip counter is started again to ensure that the counter is started accurately when the first rising edge is queried. The second is a stop interrupt, and the counting stops after the collection counting cycle overflows.

Figure 2 Software control collection count start and stop flow chart

(a) MCU query count completion flow chart (b) interrupt execution counter start and stop control flow chart

It is easy to see that the original background noise subtraction functional unit needs to interface with the MCU through many data lines, 16 in total, and because of the different on-chip resources of different microprocessors, the software operation may be more complicated and not very portable.

In summary, if the background noise subtraction functional unit is designed as an 8-bit data bus interface, the high and low bytes are time-division multiplexed, and the 16-bit binary number preset number and counting cycle can be set, and the circuit can read the counting result after the MCU gives a start signal and waits for the query completion signal, the circuit board area can be greatly reduced, the interface can be simpler, and the operability and portability can be improved.

3 VerilgHDL Design of Background Noise Subtraction Circuit

According to the top-down design idea and bottom-up implementation method, the background noise subtraction circuit can be divided into four modules: the main module (backnoise_deduct), the 16-bit binary addition and subtraction counting module (bit16addsub), the acquisition control module (Ctrol), and the read-write interface module (Addselec).

The main module is responsible for calling the other three modules and connecting the input and output interfaces. The 16-bit binary addition and subtraction counting module is responsible for adding the given preset number when the signal pulse arrives at the high level of the modulation cycle and subtracting the number when the signal pulse arrives. The acquisition control module is responsible for automatically querying the first rising edge of the modulation frequency to start counting when the MCU gives a count permission command, stopping counting after the count cycle is reached, and notifying the MCU after the count is completed. The read-write interface module is responsible for interfacing with the MCU, receiving and storing the count cycle (the number of cycles of the chopper signal or the modulation signal) and the 16-bit preset number, and returning the final count result to the MCU.

The external interface of the main module is shown in Figure 3. FREQU1, FREQU2 are sampling frequency inputs 1 and 2; CHOP_IN is the chopper or modulation frequency input, CLR is the clear signal, which is valid at a high level; cpu_alw is the enable signal issued by the MCU, which is valid at a high level; stopsign is the acquisition completion signal, which is completed at a high level; WD, RD, CS are write, read, and chip select signals; DB is an 8-bit bidirectional data bus; a2_0 is a 3-wire on-chip register address decoding selection interface.

Figure 3 External interface of the background noise subtraction main module synthesis generation schematic

The 16-bit binary addition and subtraction counting module (bit16addsub) is the specific implementation unit of the background subtraction circuit, and the code is shown below.

module bit16addsub(

input wire FREQU, // sampling frequency input

input wire CHOP_IN, //Chopper input

input EN, // start and stop control

input wire CLR, //Please zero

input wire [15:0] STA_NUM, //initial value

output reg[15:0] result_num //Count result output

);

always @(posedge FREQU or posedge CLR) //Sensitive to acquisition signal and clear signal

begin

if(CLR==1) // clear

result_num<=STA_NUM; //Re-read the preset number

else if(EN==1&&CHOP_IN==1&&FREQU==1)

result_num<=result_num+1; //When the modulated signal is high in the enabled state, count up

else if(CHOP_IN==0&&EN==1&&FREQU==1)

result_num<=result_num-1; //When the modulation signal is low in the enabled state, the count is reduced

end

endmodule

The acquisition control module (Ctrol) is the timing control core of the entire design. The ctrol it outputs is connected to the EN of the 16-bit binary addition and subtraction counting module (bit16addsub) to realize the start of automatic control counting, and stop when the counting cycle overflows. After the counting is completed, a high-level signal is given after stopsign to notify the MCU. The complete code is as follows:

module Ctrol(input wire reset, //reset signal

input wire cpu_alw, //MCU enable signal

input wire chop_in, //chopper input count

input wire [16:0] status_in, //count cycle value

output reg ctrol, //Start and stop control signal of the add/subtract counter

output reg stopsign //Counting completion signal

);

reg [16:0]num_count; //Internal counting period register

always @(posedge reset or posedge chop_in)

begin

if(reset) // reset

begin

num_count<=status_in; //Read in the counting cycle

ctrol<=0; //stop counting

stopsign<=0; //Counting is not completed

end

else if(chop_in==1&&cpu_alw==1)//Allow counting

begin

if(num_count>0) //Collection is not completed

begin

ctrol<=1; //16 add/subtract counter enable

num_count<=num_count-1; //Counting cycle minus one

end

else

begin

ctrol<=0; //Counting stops

stopsign<=1; //Notify MCU

end

end

end

endmodule

The read/write interface module (Addselec) uses a common bidirectional data bus input/output method when programming. The register address is selected through the 3-wire decoding of a2_0, and the counting cycle and preset number can be assigned, and the final counting result can be read out. Table 1 shows the register address corresponding to the decoding.

Table 1 a2_0 decoding selection truth table

FIG4 shows the simulation waveform of the write signal using ModelSim software, showing that the values ​​written into the low and high 8 bits of the last counting cycle are 00000101 and 00000000, and the values ​​of the low and high 8 bits of the preset count are 00000011 and 00000000.

Figure 4 Waveform simulation results of counting cycle and preset number when writing to the bus

4 Background noise subtraction circuit and MCU interface and software operation

Figure 5 Software operation flow of background noise subtraction circuit

The integrated background noise subtraction circuit designed above is very convenient when interfacing with MCU. Taking the MCS51 series 8051 microcontroller as an example, the simplest connection method is to use the P1 port to connect to CLR, cpu_alw, stop_sign, the address line to connect to CS, a2_0 (the chip select mode can be set according to the circuit scale), and the data line and read and write are connected normally. Software operation does not require interruption, and the operation flow is shown in Figure 5. A simpler approach is to assign fixed values ​​to the preset number and count cycle when the system is initialized.

5 Conclusion

This paper introduces the implementation principle and working mode of the background noise subtraction circuit composed of counter and gate circuit, analyzes its limitations, and then proposes a design of background noise subtraction circuit based on VerilogHDL language, which makes the circuit interface simpler, the software easier to operate, and enhances portability. This design has been applied to the ultraviolet remote sensing instrument under development, providing technical support for the upgrading of the instrument. The design of the background noise subtraction circuit designed in this paper based on versatility and simplicity will be suitable for the scheme of converting weak DC quantity into AC signal measurement by photoelectric modulation.

The author's innovation point: Aiming at the limitations of the original background noise subtraction functional unit, a background noise subtraction circuit with convenient interface and easy operation is designed using VerilogHDL language, making it have strong versatility and applicability.