RS485 interface circuit and test circuit for automatic transceiver conversion

The dotted box shown in Figure 1 is the interface circuit . By analyzing the truth table, its sending and receiving process is as follows:

When DI=0 at the transmitting end, DE/RE=1 transmits a 0 level, and RO=0 at the receiving end; when DI=1 at the transmitting end, DE/RE=0, VA=VB=2.5V, RO=1 at the receiving end due to the pull-up resistor .

A 1kHz TTL square wave is added to the TXo end of this interface circuit to test the circuit. When the 120Ω terminal resistor is not added, the voltage change process of the 485-A and 485-B pins of the interface chip is about 50μs, as shown in Figure 2. The rising edge of the Ro waveform at the receiving end has a significant delay of about 30 to 40μs (compared with the data transmitting end DI), causing a large transmission error; when the 120Ω terminal resistor is added, the delay is significantly reduced to about 3μs.

When this circuit sends a high level, the transmitter is in a high impedance state, all interfaces on the bus are in a receiving state, the bus is idle, and other interfaces are allowed to send data, so it is easy to introduce bus conflicts. Especially when sending high-level bits continuously, the longer the transmitter is in a high impedance state, the greater the probability of introducing bus conflicts.