MT8888 chip is a low-power, high-integration DTMF signal receiving and transmitting chip produced by MITEL using CMOS technology. It can be easily interfaced with a microcomputer. This paper introduces the main functional structure and control instructions of MT8888 and gives its specific application circuit.
Keywords: DTMF signal transceiver, low power consumption, programmable microcomputer control, MT8888
1 Overview
MT8888 is a DTMF signal transceiver integrated circuit produced by CMOS technology. Its transmitting part adopts a switched capacitor D/A converter with low signal distortion and high frequency stability, and can send 16 kinds of dual-tone multi-frequency DTMF signals. The receiving part is used to complete the reception, separation and decoding of DTMF signals, and output them in the form of 4-bit parallel binary code. MT8888 chip has high integration and low power consumption. It can adjust the duty cycle of dual audio mode, automatically suppress dial tone and adjust signal gain. It also has a standard data bus, is compatible with TTL level, and can be easily programmed and controlled.
2 Pinout and Function
The pin arrangement of the MT8888 chip is shown in Figure 1; the functions of each pin are as follows:
IN+: op amp non-inverting input terminal;
IN-: op amp inverting input terminal;
GS: op amp output;
VREF: reference voltage output terminal, voltage value is VDD/2;
Vss: ground terminal;
OSC1: oscillator input terminal;
OSC2: oscillator output terminal;
TONE: DTMF signal output terminal;
WR: write control terminal, low level is effective, compatible with TTL;
CS: chip select terminal, low level is valid;
RSO: memory selection input, compatible with TTL;
RD: read control terminal, low level is valid, compatible with TTL;
IRQ/CP: interrupt signal request terminal;
D0~D3: Data bus, when CS=1 or RD=1, it is in high-impedance state and compatible with TTL level.
Est: initial control output terminal;
St/GT: control input/time detection output;
VDD: +5V power supply terminal.
3 Internal structure
MT8888 is composed of transceiver circuit, oscillator and power bias circuit. The receiving circuit includes signal amplification, dial tone suppression filtering, high and low frequency bandpass filtering of input signal, decoding and latching functions; the transmitting circuit includes data latching, row and column counting D/A conversion and mixing functions. The internal structure of MT8888 is shown in Figure 2.
4 Registers and Control
There are two data registers inside MT8888, one is the receive data register RDR which only performs read operations; the other is the transmit data register TDR which only performs write operations. In addition, there are two 4-bit receive and transmit control registers CRA and CRB in MT8888. The operation of CRB is operated through a specific bit in CRA, so it should be initialized during programming; and the 4-bit status register SR in MT8888 is used to reflect the working status of the receive and transmit signals. The selection and operation of the registers are controlled by RS0 and the WR and RD port lines. The control functions are listed in Table 1.
Table 1 Register control function table
RS0 | WR | RD | Function |
0 | 0 | 1 | Write transmit data register |
0 | 1 | 0 | Read receive data register |
1 | 0 | 1 | Write Control Register |
1 | 1 | 0 | Read Status Register |
MT8888 can provide three working modes when sending signals, namely DTMF mode, burst mode, and CP mode. These three working modes can be set through registers. The functions of each register are listed in Table 2 and Table 3.
Table 2 Control Register Function Table
Control Register | Control bit | Name | Function | illustrate |
CRA | b0 | Tout | Signal tone output control | Logic "1" enables the signal tone output |
b1 | CP/DTMF | Mode Control | Logic "1" is CP mode, logic "0" is DTMF mode | |
b2 | IRQ | Interrupt Enable | Logic "1" enables interrupt mode. When b0 = 1, the DTMF/CP pin level changes from high to low after receiving a DTMF signal or sending a DTMF dual-tone signal. | |
b3 | RSEL | Register Selection | Logic "1" The next time register CRB is accessed, the access structure is transferred back to register CRA | |
CRB | b0 | BURST | Dual-tone burst mode | Logic '0' enables dual tone burst mode |
b1 | TEST | Test Mode | Logic "1" enables test mode to output a delay control signal on the IRQ/CP pin | |
b2 | S/D | Single and double tone generation | Logic "0" allows the generation of DTMF signals, otherwise a single tone is output | |
b3 | C/R | Column/Row Tone Selection | When b2=1, logic "0" enables the generation of row tone signal logic, and logic "1" enables the generation of column tone signal. |
Table 3 Status register function table
Status Bits | Name | Status flag set | Status flag cleared |
B0 | IRQ | An interrupt occurs; b1 or b2 = 0 | Read Status Register Clear |
B1 | Transmit register empty (burst mode) | Pause ends: prepare to send table data | Read Status Register Clear |
B2 | Receive register full | The data of the receiving register is valid | Read Status Register Clear |
B3 | DTMF signal flag | Set when no DTMF signal is detected | Detect DTMF signal cleared |
5 Application Circuit
The peripheral circuit of MT8888 is very simple, and it is also very convenient to interface with the microcomputer. The gain of the input signal can be adjusted by changing R2. The specific application circuit is shown in Figure 3.
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