Single-ended input driver circuit for differential input intermediate frequency sampling ADC

Publisher:Yinyue1314Latest update time:2011-01-11 Keywords:ADC Reading articles on mobile phones Scan QR code
Read articles on your mobile phone anytime, anywhere

Circuit Function and Advantages

The circuit shown in Figure 1 uses the ADL5535/ ADL5536 single-ended intermediate frequency (IF) low noise 50 Ω gain block to drive the AD9268 16-bit differential input analog-to-digital converter (ADC). The circuit includes an interstage band-pass filter for noise reduction and anti-aliasing. The single-ended IF gain stage is followed by a transformer to perform the single-ended to differential conversion. This is the optimal solution for applications that require low noise and low distortion.

The ADL5535/ADL5536 are highly linear (OIP3 = +45 dBm, third-order output intercept at 190 MHz), single-ended, fixed-gain amplifiers that can be used as drivers for high performance IF sampling ADCs. The ADL5535 provides 16 dB of gain, easily boosting the signal from approximately 400 mV pp to the 2 V pp full-scale level required by the ADC. The low noise figure (3.2 dB at 190 MHz) and low distortion of the ADL5535 ensure that the ADC performance is not compromised. When a gain of 20 dB is required, the ADL5536 can be used.

ADL5535 drives 16-bit ADC AD9268

Figure 1. ADL5535 driving the AD9268 16-bit ADC (simplified schematic, decoupling and all connections not shown)

Circuit Description

Figure 1 shows the schematic diagram of the ADL5535/ADL5536 driving the AD9268 16-bit ADC with a sampling rate of 122.88 MSPS. The ADL5535 has a single-ended input and output impedance of 50 Ω. A 1:1 impedance transformer (M/A-COM BA-007159-000000, 4.5 MHz to 3000 MHz) is used with termination resistors and series ferrite beads to provide a 50 Ω load to the antialiasing filter interface. The filter interface between the ADL5535 and the AD9268 is a sixth-order Butterworth low-pass filter designed using a standard filter program. It provides a 50 MHz, 1 dB bandwidth centered at 175 MHz. A shunt LC (72 nH, 8.2 pF) tank circuit is used after the sixth-order filter to further reduce the low frequency response of the filter, giving the filter a more bandpass response. The normalized broadband response is shown in Figure 2.

Normalized frequency response of the ADC interface shown in Figure 1

Figure 2. Normalized frequency response of the ADC interface shown in Figure 1.

For an input frequency of 170 MHz and a sampling rate of 122.88 MSPS, the single-tone performance is shown in Figure 3 and the two-tone performance is shown in Figure 4.

Single-tone performance of the circuit shown in Figure 1 measured at an input frequency of 170 MHz and a sampling rate of 122.88 MSPS

Figure 3. Single-tone performance of the circuit shown in Figure 1 measured at an input frequency of 170 MHz and a sampling rate of 122.88 MSPS.

Two-tone performance of the circuit shown in Figure 1 measured with an input tone centered at 170 MHz and a sampling rate of 122.88 MSPS

Figure 4. Two-tone performance of the circuit shown in Figure 1 measured with an input tone centered at 170 MHz and a sampling rate of 122.88 MSPS.

Common Changes

The application circuit described in this article can be modified for any IF frequency within the operating range of the ADL5535/ADL5536 and AD9268. The AD9640, the AD6657, or the AD9* can replace the AD9268 ADC in this application.

Keywords:ADC Reference address:Single-ended input driver circuit for differential input intermediate frequency sampling ADC

Previous article:Design and implementation of 12-bit high-speed ADC storage circuit
Next article:Design of RS232 serial port A/D analog-to-digital conversion digital tube

Recommended ReadingLatest update time:2024-11-16 23:49

10 factors that must be considered when working together with DSP and data converters
Suppose you receive a task to design a signal processing system composed of DSP, DAC, ADC and other analog devices. The job is pretty simple if you take a few important factors into consideration. Let’s talk about these factors that should be considered in design work. Learn more about application types The first s
[Analog Electronics]
Differential Driver for Precision ADC
Differential Input ADC Characteristics One of the most common ways to drive a differential input ADC is to use a transformer. However, because the frequency response must extend to DC in many applications, transformers cannot be used. These situations call for a differential driver. This tutorial focuses
[Analog Electronics]
Differential Driver for Precision ADC
Discussion on STM32F4 four-channel ADC sampling problem
1.ADC configuration 1.1 Mode determination Master-slave mode, select the master ADC1 mode to drive the slave ADC2 mode Corresponding code snippet: /* Enable DMA request after last transfer (Multi-ADC mode)  */ ADC_MultiModeDMARequestAfterLastTransferCmd(ENABLE); 1.2 Clock Initialization ADC The ADC clock is on
[Microcontroller]
Discussion on STM32F4 four-channel ADC sampling problem
Interesting talk about STM32 ADC and DMA
Recently, I was working on ADC sampling battery voltage, and sometimes I was a little confused. I can collect the voltage well without DMA, so why should I spend all that effort to use DMA? What if I make a mistake with DMA? The effect of not using DMA has not affected me to the point where I have to use it. Sometimes
[Microcontroller]
Interesting talk about STM32 ADC and DMA
Oversampling Interpolation DAC
Introduction Oversampling and digital filtering can help to reduce the requirements on the antialiasing filter preceding the ADC. Reconstruction DACs can use the principles of oversampling and interpolation in a similar manner. For example, digital audio CD players often use oversampling, where the basic data updat
[Analog Electronics]
Oversampling Interpolation DAC
ADC key performance indicators and misunderstandings
Since the demand for ADC products is much smaller than that for network products and servers, users and integrators inevitably have some misunderstandings about key indicators when choosing products. In addition, some mainstream manufacturers deliberately guide that many non-key indicators in bidding specific
[Analog Electronics]
STM8S——Analog/digital converter (ADC)
1. ADC1 and ADC2 are 10-bit successive approximation Anolog to Digital Converters. The so-called successive approximation means successive approximation; 2. ADC is divided into ADC1 and ADC2. The function of ADC1 is more powerful than ADC2. We use ADC1. 3. ADC has multiple modes: (1) Single mode (2) Continuous
[Microcontroller]
STM32 ADC single channel continuous routine
#include "stm32f10x.h" /*RCC clock configuration*/ void RCC_config(void) {  ErrorStatus HSEStartUpStatus; /* RCC registers are set to default configuration */ RCC_DeInit(); /* Turn on external high speed clock */ RCC_HSEConfig(RCC_HSE_ON); /* Wait for the external high-speed clock to stabilize*/ HSEStartUpStatus
[Microcontroller]
Latest Analog Electronics Articles
Change More Related Popular Components

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号