Low Power High Slew Rate CMOS Analog Buffer

Introduction: Analog voltage buffers are very important basic building blocks in mixed signal design. They are mainly used for signal monitoring and driving loads. In the first case, the buffer is usually connected to the internal node of the test circuit and the circuit that requires low input capacitance, because any increase in parasitic capacitance at this node may be critical. However, when the buffer is used to drive the load, we want a high slew rate within a large range of output signal swings in order to drive the load as quickly as possible over the entire power supply voltage range.

The supply voltage of integrated circuits has been reduced, mainly focusing on power consumption and reliability issues. This trend has forced the redesign of most analog building blocks to try to ensure their overall performance. Under these design constraints, rail-to-rail operation has become mandatory in low-voltage designs in order to increase the signal-to-noise ratio.

In this article, I introduce a circuit technique that can achieve class AB characteristics of a rail-to-rail CMOS analog buffer, resulting in a method with low power consumption and high drive capability.

Previous complementary: Figure 1a shows a P-channel class AB differential pair that can carry very large currents when a large differential signal is applied to the input. The impedance at the differential pair node A is very low, and its voltage is approximately constant even under large input signals. Therefore, the differential voltage V1-V2 produces a large current change on M2, and the same is true for M3.

A class AB voltage buffer can be obtained by connecting two complementary differential cells, as shown in Figure 1c. Undoubtedly, the circuit in Figure 1c has two limitations. First, the gate-source voltage of M3P and M3N can force the driver transistors M1P and M1N to operate in the triode region, respectively, reducing the available voltage operating range. This defect can be overcome by introducing a voltage level shifter to drive M3P and M3N, which will be explained later. Second, the output voltage swing of this structure is limited when the output node is close to the positive or negative power rail. This is mainly due to the limitation of the P-channel and N-channel differential pairs operating at VDD and VSS, respectively.

Figure 1 Class AB differential input cell; DC transmission characteristics of differential signals; low-power buffer based on two pairs of complementary class AB differential input cells

a Class AB differential input unit b DC transfer characteristics c Low power buffer

Proposed Analog Buffer: Figure 2 shows the transistor-level implementation of the proposed rail-to-rail MOS analog buffer. This circuit is a single gain stage. Its input branch consists of two complementary class AB differential pairs. The important difference from the circuit in Figure 1c is that in this case, the output nodes are not driven directly by the input driver, but by current mirrors M4P-M5P and M4N-M5N respectively. Therefore, the common gate of M2P and M2N is now the non-inverting input terminal.

Figure 2 Proposed rail-to-rail class AB buffer

In the mid-supply voltage region, the PMOS and NMOS input pairs are active, and their bias currents are mirrored to the output of the circuit through current mirrors M4P--M5P and M4N--M5N. This structure allows the NMOS input pair to drive the output node in the supply voltage region close to VDD. While the PMOS controls the voltage range of the output terminal close to VSS. Unfortunately, near VDD, the P-channel input pair is cut off, and no current is mirrored to the bottom of the output terminal, turning off the buffer. A similar situation is at VSS. The N-channel differential pair is not active. For this reason, transistors M1PR-M5PR and MlNR-M5NR have been included in Figure 2 to maintain active over the entire voltage range.

Therefore, the operation of this buffer can be described in detail as follows: When the input signal Vin is in the mid-supply voltage region, the two input pairs MIP~M2P and MlN-M2N are effective, and M4P-M5P and M4N--M5N mirror a current equal to IB to the output branch. Moreover, the replica of the current IB is copied through transistors MIPR (M1NR) and M2PR-M3PR (MlNR-M2NR) to provide current to the current source of the additional circuit at the bottom of the output branch. Therefore, transistors M4P and M5P (M4N and M5N) are turned off and do not contribute to the output current. When the input signal is close to VDD, the PMOS input pair is turned off, and the replica of the inverting input branch and so on are all turned off. MIPR--M3PR does not send any current to the additional circuit of the output branch. In this case, M4PR and M5PR are turned on, absorbing a current equal to IB from the output branch to keep the buffer conductive. A similar situation occurs when the input signal Vin is close to VSS.

It should be noted that voltage level shifters have been included in the input stage in order to drive M3P and M3N in the linear region and beyond the input signal range to avoid M1P and M1N working separately. Therefore, rail-to-rail operation is achieved at the input as well as at the output of the circuit.

The dynamic operation of the proposed buffer can be improved by the high driving capability of the class AB differential pair in the circuit input branch. Upon encountering a large positive input signal, transistor M2P is turned off, while M2N absorbs a large current, which is mirrored to the output section through M4N and M5N. Conversely, when a large input signal is applied in the negative direction, transistor M2N is turned off, and M2P transmits a large current, which is copied to the output section through M4P and MSP.

The input capacitance of the proposed buffer can be reduced by proportionally reducing the size of transistors M2P and M2N. Needless to say, it must be pointed out that the reduction in the aspect ratio of these transistors leads to a reduction in their effective driving capability. Besides, there is only one high impedance node in such a circuit and its bandwidth can be very large. However, a single gain stage structure with a high output impedance at the output node is very suitable for driving large capacitive loads, assuming a low resistive load that reduces the overall gain of the buffer. , therefore, it is accurate.

Figure 3 DC transfer characteristics of the simulated buffer in Figure 2

Simulation results: The analog voltage buffer in Figure 2 has been designed and implemented in 0.35uCMOS process. The operating power supply voltage is 1.5V, the bias current is 10uA, and the load capacitance is 10pF.

Figure 3 shows the DC transfer characteristics of the proposed analog buffer with offset voltage. As expected, the rail to rail characteristic is achieved. Figure 4 shows the large signal transient response of the circuit of Figure 2. In particular, the output voltage reveals the high slew rate due to the class AB operation at the input stage. However, the large ratio of the maximum current to the quiescent bias current through the output transistor confirms that the proposed approach results in low power consumption and high drive capability.

For the simulation with DC input voltage equal to zero, the open-loop gain and unity gain frequency are approximately 54dB and 6.1MHz. The relatively low gain value is due to the circuit being a single gain stage. The gain-bandwidth value comes at the expense of increased bias current of the input differential pair. Therefore, power consumption is increased. For a 2.4VPP 100kHz input sinusoidal signal, an ATHD of -44.6dB is obtained. When the input resistance is not reduced proportionally, the simulated capacitance of the proposed buffer is reduced by 32fF.

Figure 4 shows the large signal transient response of the simulated buffer in Figure 2 for a 2.4VPP 1MHz square wave input signal and a 10pF load capacitor.

a Input and output voltages b Current through the output transistor

Conclusion: A rail-to-rail voltage buffer with reduced input capacitance has been proposed. Rail-to-rail operation is achieved not only at the output of the circuit but also at the input of the circuit. The AB characteristics of the presented circuit result in low power consumption and high slew rate, making it suitable for driving large capacitive loads. Simulation results have been provided for the operation of the circuit.

The author's innovation: A rail-to-rail voltage buffer with reduced input capacitance is proposed. Rail-to-rail operation is achieved not only at the output of the circuit, but also at the input of the circuit. The AB characteristics of the circuit introduced result in low power consumption and high slew rate, making it very suitable for driving large capacitive loads. Simulation results have provided the operation of the circuit.