A VCO with lumped LC components is used to form a 155.520MHz phase-locked clock frequency source.

    Abstract: This paper introduces a narrowband voltage-controlled oscillator (VCO) built with MAX2620, and on this basis introduces its design scheme to build a 155.520MHz point frequency phase-locked clock source dedicated to SDH together with the phase-locked loop chip Q3236. This clock source has the characteristics of low noise, high stability, low cost and good application prospects.

    Keywords: clock source SDH phase-locked loop voltage controlled oscillator (VCO)

As a transmission system, SDH has been widely used in our country. At present, most of the domestic SDH backbone networks are 10G optical fiber networks. With the development of optical communication technology, the transmission rate will continue to increase. The SDH network synchronization structure usually adopts the master-slave synchronization method, which requires that the timing of all network element clocks can ultimately track the reference master clock of the entire network. ITU-T has strict regulations on the clock parameters of each SDH node, such as the center frequency of the clock, frequency accuracy, stability, clock jitter and drift, etc., as well as the pull-in range, pull-out range, and hold range [1] . In the SDH system, the 155.520Mbit/s synchronous transmission module (STM-1) is used as the basic information module, and the high-rate signal is the synchronous multiplexing of N STM-1 signals to form STM-N[2] , so the 155.520MHz clock source is widely used as the network element timing clock in the SDH network. This article will introduce how to use the integrated circuit MAX2620 and integrated LC components to form a narrow-band VCO circuit module, and then together with the phase-locked loop chip Q3236 to form a phase-locked loop type low-noise, high-stability 155.520MHz clock circuit.

1 Circuit scheme design

Figure 1 shows the basic circuit composition of a phase-locked loop (PLL) [3]. Among them, REF represents the reference signal source, 1/R is the reference source frequency divider, PD is the phase detector, LF is the loop filter, VCO is the voltage controlled oscillator, and 1/N is the N frequency divider.

The 155.520MHz VCXO (Voltage Controlled Crystal Oscillator) dedicated to SDH is available abroad, but there are very few domestically produced ones and the price is relatively expensive. General VCO devices, such as 100MHz ~ 200MHz, 75MHz ~ 160MHz, 140MHz ~ 170MHz and other devices launched by Varil, Mini, Vectron, Mti, MicroNetworks and other companies are used in wide frequency bands. The clock source in SDH is a fixed point frequency, such as STM-1 is 155.520MHz. Therefore, it is not suitable to use the above wide-band VCO to design this point frequency circuit. This requires designing a narrow-band and phase noise performance Superior VCO. Although discrete transistors, resonant circuits and buffer amplifiers can be used to form a VCO circuit, compared with IC chips, they have poor stability, are greatly affected by power supply and distribution parameters, and are inconvenient to debug. MAXIM's MAX2620 is an integrated oscillator chip that can work in a wide frequency range (10 ~ 1050MHz). It has the characteristics of low flicker noise, low noise figure and low parasitic rb unique to high-frequency bipolar technology. Users can configure an appropriate oscillation circuit according to their own needs and design a voltage-controlled oscillator circuit with the required center frequency. The internal active devices of the MAX2620 place an extremely light load on the resonant circuit, so that the resonant circuit has a high loaded Q value, so it can be used to design a narrow-band voltage-controlled oscillator circuit with a frequency of 155.520MHz.

It can be seen from the phase noise theory that the larger the frequency division ratio in the phase-locked loop, the greater the loss of the phase noise indicator from input to output, so the phase detection frequency of the clock circuit is set to 19.440MHz, so that the phase detection frequency As high as possible, the phase-locked loop frequency division ratio is small. Conventional PLL integrated circuits such as Motorola's MC14515X series have a maximum phase detection frequency of 2MHz and are not applicable. QualComm's Q3236 has a phase detection frequency that can reach hundreds of MHz and can be used in this design.

2 155.520MHz VCO design

MAXIM Company's MAX2620 is an extremely easy-to-use oscillator chip. Its internal composition diagram [4] is shown in Figure 2.

The MAX2620 provides a buffered amplifier output stage that reduces the impact of load changes on the oscillator frequency. The power supply voltage range is between +2.7V and +5.25V. There is an internal bias circuit to stabilize its operating point, so that the operation is less affected by power supply fluctuations. It also has the ability to shut down the power supply and is controlled by the SHDN terminal. Two complementary outputs (i.e. OUT and OUT) can form two single-ended outputs or a differential output. Since it is an open-collector output, the output needs to be pulled up to Vcc. The pull-up can be done with an inductor or resistor, but for differential outputs it should be done the same way on both ends. For a 50 Ω load, when using an inductor to pull up, the single-ended output level can reach -6dBm (peak-to-peak voltage is 320mV); when using a resistor to pull up, the output can reach -10dBm (200mV). In this design, one of the two outputs of the MAX2620 is output to the PLL for phase detection. In order to ensure good stability, this circuit is pulled up with a resistor. The other output is buffered and amplified and used as a clock output. In order to make its output power high, it is pulled up by an inductor.

    MAX2620 needs to be connected to an external RF resonant tank to form a VCO circuit, as shown in Figure 3.

The form of this circuit is a typical Colpitts common collector topology. This topology can work in a wide frequency range, from intermediate frequency to radio frequency [4]. The MAX2620 manual states that its operating frequency range is 10MHz ~ 1050MHz. The resonant circuit is on the left side of Figure 3, connected through pin (2) and pin (3), and mainly includes capacitors C0 ~ C4, resonant inductor L1, varactor Cvar, and the tuning voltage is connected through resistor Rt.

For a voltage controlled oscillator with a 155.520MHz point frequency clock source, a wide tuning range is not required. Taking advantage of this, the varactor can be connected to the resonant circuit through C0. To alleviate coupling, the C0 value is taken to be 1.8pF. The variable capacitor Cvar can be selected from the flexible MV2107, Cvar=22pF (capacitance at -4V bias). Qmin=350 at 50MHz, converted to 155MHz, Q is about 115. After C0, the equivalent Q of the resonant circuit increases by at least 5 times, achieving the goal of designing a resonant circuit with higher Q even if a cheap varactor with lower Q is used.

The resonant circuit inductor adopts a surface-mounted resonant inductor, which has the characteristics of small radiation interference, small influence by distributed capacitance, and easy debugging. The inductance value is selected as 47nH. When the resonant frequency is 155.520MHz, the total capacitance of the resonant circuit CT=22.34pF is obtained from the resonance formula f=2π ( the root of LCT). After debugging, the specific component parameters of the VCO circuit are as follows:

Rt=1～3k Ω, Cvar uses MV2107 varactor, resonant inductor L1-=47nH, C0=1.8pF, C1=18pF, C2=5pF, C3=6.8pF, C4=4.3pF, the output terminal OUT is pulled up The inductor L2 is 100nH, and the pull-up resistor RO=50 Ω at the output terminal OUT .

3 Introduction to the phase-locked loop chip Q3236 and its loop filter design

QualComm's Q3236 is a digital phase-locked loop chip with programmable frequency division times that can operate in the frequency band up to 2GHz and consumes less than 0.6W under normal operating conditions. Its internal voltage [6] is shown in Figure 4.

The reference signal (REFIN) and VCO feedback signal (FVCO) input terminals can be set to differential input or single-ended input, and have high input sensitivity. The level requirement is -10dBm ~ +5dBm, and the input impedance is 50 Ω .

When the frequency divider with built-in VCO works in the pre-scaler mode, the operating frequency can be as high as 2GHz. The total frequency division N is completed by a swallowing pulse counter composed of an internal 10/11 prescaler, a 4-bit low-order A counter, and a 9-bit high-order M counter. When no prescaler is used, the operating frequency of Q3236 is up to 300MHz. 1/R is the reference source divider. There are three setting modes for the Q3236 divider: serial mode, 8-bit bus mode and parallel direct setting mode.

Q3236 requires an external loop filter. A first-order active proportional low-pass filter is used in this design, as shown in Figure 5.

The low-noise operational amplifier TLE2037 and R and C components are used to form a loop filter. The values ​​of R, C and other components are calculated from the phase-locked loop parameters.

A known:

In the formula: τ1=(kdk0)/Nωn

τ2=2ξ/ωn

For the point frequency clock circuit, the stability is high, so the phase-locked loop 3dB bandwidth B3dB=1kHz and the damping coefficient ξ=0 are selected.

707 . It is known that the phase identification coefficient of Q3236 kd=302mV/rad, and the voltage control sensitivity of the VCO at 155.520 k0=2 π×80rad/sV . Under the condition that C=0.1 μF and the pre-filter cutoff frequency is 2.5kHz, substitute the above formula to calculate the component value as follows:

R1/2=10k Ω ; R2=4.3k Ω ; Cp=0.02 μF .

4 Phase-locked clock circuit

Based on the above analysis and design of each part of the phase-locked loop circuit, the following phase-locked clock circuit scheme can be designed, as shown in Figure 6.

The actual circuit is made on a 72mm×72mm double-layer board, and the power supply voltage is +5V. The frequency coverage of the VCO is 155.400043MHz ~ 155.646042MHz. The voltage control sensitivity ko at 155.520MHz is 2 π×80krad/sV . The two output levels are -6dBm at the OUT end and -10dBm at the OUT end. Using a high-stable integrated signal source as the reference signal, the measured clock source output is 155.52000MHz, the output power is ≥10dBm, the signal purity is high and there are few spurious.

    The narrowband VCO composed of lumped LC components and MAX2620 has the advantages of high stability, little influence from external distribution parameters, easy debugging, small size, and low price. The VCO and Q3236 chip form a phase-locked loop 155.520MHz point frequency clock source, operating at a phase detection frequency of up to 19.440MHz, which reduces the deterioration of the phase noise from input to output. The test results show that the clock source has high frequency stability and low phase noise. This lays the foundation for the miniaturization and mass production of SDH clock equipment.