Network switch box circuit

    Network switching products typically use a large number of FIFOs to convert data from one network terminal to another terminal switch. Using dual FIFOs in such applications can save board space.

   Figure 1 shows the circuit design of the network switch box. It can be seen from the figure that a FIFO switch is used to convert data between any input and output buses. Data flow is one-way. The dual FIFO is not only used to buffer data, but also to control the address usage of the central data memory. In Figure 1, 4 input paths and 4 output paths are shown; however, the design structure can be easily expanded to accommodate as many buses as desired. The network switch box designed with IDT's 728×1 FIFO has the ability to switch a 9-bit wide bus, while the network switch box designed with 728×5 has the ability to switch an 18-bit bus.

    Use a FIFO bank to buffer input data, one FIFO for each input bus (in Figure 1, the "source FIFO" is represented by A, B, C, D). Another FIFO memory bank is used to buffer output data, with one FIFO for each output bus (in the figure, the "terminal FIFO" is represented by 1, 2, 3, 4).

    The SRAM data storage unit is used to hold information units that have been received through the source FIFO and are waiting to be transferred to the terminal FIFO. For example, an ATM information unit generally consists of a 5-byte header (including address information) and a 48-byte data string. Network switch boxes will handle these units differently. In order to process unit information more efficiently, SRAM can be divided into header area and data area.

    The "FreeAddress" FIFO keeps track of free address locations in the SRAM bank.

    The last FIFO unit is called "Available Cell", which keeps track of the cells stored in SRAM and waits to be booted to the terminal FIFO. Each "Available Cell" FIFO supports an output data bus and holds the address of the SRAM connected cell for that particular bus. In Figure 1, the four "Available Cell" FIFOs are numbered 1, 2, 3, and 4.

    The microcontroller monitors the status of the switch box, assigns addresses and controls data flow.

    The network switch function is: after receiving at least one data unit, the programmable quasi-full ( ) flag of the source FIFO is set to a low state. The processor periodically checks the flags of each source FIFO. Once a unit is written to the source FIFO, the associated flag goes low to indicate that the data is valid. The processor obtains a valid SRAM address from the free address FIFO, then reads the location from the source FIFO and writes it to the SRAM at the selected free address. Once this process is complete, the processor accesses the unit's header from the SRAM and identifies which terminal FIFO collected the data for decoding and updating the header. The processor then writes the cell's SRAM address to the corresponding Available Cell FIFO in the terminal FIFO.

    As long as sufficient space is available for a cell to register data, the terminal FIFO's programmable quasi-empty ( ) flag is set to a low state. The processor periodically checks the flags of each terminal FIFO. As long as space is available for a terminal FIFO, the relevant flag goes low. The processor obtains an address from the corresponding Available Cell FIFO of the terminal FIFO and uses it to lock a cell stored in SRAM memory. Finally, the processor passes the unit to the appropriate terminal FIFO and writes the new free unit address into the Free Address FIFO.