Circuit Description

For analog signals, most SAR ADCs require a suitable input buffer for optimal performance. The buffer isolates the signal source from the transients generated at the ADC input when the internal sample-and-hold switch switches from hold to sample. The buffer driving the ADC must recover from this transient and settle to the required accuracy within the ADC acquisition time. This is especially important in applications where the signal source has high impedance and low distortion and high signal-to-noise ratio are critical. Therefore, choosing the right buffer op amp becomes a very important part of the design.

The AD7091R is a 12-bit, fast, ultra-low power, single-supply ADC with an integrated 2.5 V internal reference. The device can be powered from a 2.7 V to 5.25 V supply. The AD7091R has a throughput rate of up to 1 MSPS. When the input signal is 10 kHz and the sampling rate is 1 MSPS, the total power consumption of the device is approximately 2.3 mW.

In applications that do not require a 1MSPS sampling frequency, this number will decrease because the power consumption of the AD7091R is proportional to the throughput rate, as shown in Table 1.

The power consumption can be further reduced by reducing the throughput rate of the converter. Table 1 shows the typical power consumption of the AD7091R versus the throughput rate when the supply is 3 V and the device is operating in normal mode.

Table 1 shows the power reduction that can be achieved by activating shutdown mode. When the AD7091R is operating at lower throughput rates, shutdown mode is extremely effective in significantly reducing the power requirements.

The AD7091R is available in a small 3 mm × 2 mm, 10-lead LFCSP or a 3 mm × 5 mm, 10-lead MSOP package, both of which offer significant space savings over competing solutions.

The AD8031 is a low power rail-to-rail input/output operational amplifier that is a very suitable driver amplifier for the AD7091R. The AD8031 operates from a 2.7 V to 1 V supply, allowing two ICs to be driven from one supply rail. The AD8031 has an 80 MHz bandwidth, a 30 V/μs slew rate, and a settling time of 125 ns to 0.1% accuracy.

When operating from a single supply, the output of the AD8031 can reach within 20mV of the negative rail. If linearity with a 0V input is required, the AD8031 requires an additional negative supply (see Tutorial MT-035).

Figure 1 shows a simplified circuit diagram. Use 100 nF and 10 μF ceramic capacitors to achieve good ground decoupling of the IC power pins. Place these capacitors as close as possible to the power pins of both ICs.

It is important to remember that the analog input signals to this ADC cannot exceed the supply rails by more than 300 mV. If the signal exceeds this level, the internal ESD protection diodes will become forward biased and begin conducting current into the substrate. The diodes can conduct a maximum current of 10 mA before causing irreversible device damage. This can be achieved by connecting a pair of Schottky diodes between VIN and the AD7091R's power rails, as described in Tutorial MT-036.

The AD7091R integrates an internal 2.5 V reference. Good decoupling of the REF _IN /REF _OUT pins achieves the specified performance. The typical value of the REFIN/REFOUT capacitor is 2.2 μF. Note that the internal reference voltage can be applied externally. If an external reference voltage is used, it must be in the range of 2.7 V to VDD and must be connected to the REFIN/REFOUT pins. The typical value of the regulator bypass (REGCAP) decoupling capacitor is 1 μF.

The voltage applied to the V _DRIVE input controls the logic level voltage of the serial interface. Connect this pin to the supply voltage of the logic family that is connected to the AD7091R digital output. V _DRIVE can be set to a value in the range of 1.8 V to VDD. The typical value of the V DRIVE decoupling capacitor is 100 nF in parallel with 10 μF. If a busy indicator function is required, a 100 kΩ pull-up resistor can be connected between V _{DRIVE and the SDO pin.}

The AD8031 used to buffer the analog input of the AD7091R is configured as a unity gain buffer. A single-pole RC filter is connected after the output stage of the op amp to reduce out-of-band noise. The cutoff frequency of the RC filter is set to 660kHz. However, this parameter may be different depending on the system throughput requirement. For systems where the AD7091R is not operating at the maximum throughput rate, the filter cutoff frequency can be reduced. Depending on the input amplitude and offset of the analog signal, the AD8031 op amp can be configured to provide gain, attenuation, and level shifting to match the input signal swing of the ADC analog input range.

Table 1. Typical power consumption vs. throughput rate for the AD7091R at 3 V, normal mode

Figures 2 and 3 show the integral nonlinearity (INL) and differential nonlinearity (DNL) curves for the circuit. Note that the INL and DNL are less than ±1 LSB. 

Figure 2. INL at 1 MSPS sampling rate.

Figure 2. INL at 1 MSPS sampling rate.

Figure 3. DNL at 1 MSPS sampling rate.

Figure 4 shows the FFT data calculated for 8192 samples; the sampling rate is 1MSPS and the analog input frequency is 10 kHz. The SNR is 70.44 dBFS. 

Figure 4. FFT of the system, input = 10 kHz, sampling frequency = 1 MSPS

Figure 4. FFT of the system, input = 10 kHz, sampling frequency = 1 MSPS

The circuit must be constructed on a multilayer printed circuit board (PCB) with a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance (refer to Tutorial MT-031, Tutorial MT-101, and the CN-0247 Design Support Package for the AD7091R evaluation board layout).

Depending on the specific requirements of the application and sensor, the component values ​​around the AD7091R and AD8031 can be changed. For example, the buffer can be configured to provide gain and offset, and the cutoff frequency of the RC filter can be changed based on the sampling frequency and input frequency.

For a complete documentation package including schematics, board layout, and bill of materials (BOM), refer to http://www.analog.com/CN0247-DesignSupport

Circuit Evaluation and Testing

To evaluate and test the AD7091R and the circuit described in this circuit note, an evaluation board, EVAL-AD7091RSDZ, was developed. For detailed schematics and user guide, refer to the EVAL-AD7091RSDZ documentation. Figure 5 shows a functional block diagram of the test setup.

Equipment Requirements

To test this circuit, the following equipment is needed:

set up

Before connecting any hardware, ensure that the connections on the EVAL-AD7091RSDZ board are located as follows:

Afterwards, connect the hardware and install the software as described in the evaluation board documentation.

Refer to the evaluation board documentation for a complete description of how to run the various tests described in this circuit note. 

Figure 5. Test setup functional block diagram

Figure 5. Test setup functional block diagram