ADI's High Intermediate Frequency Sampling Receiver Front End with Integrated Bandpass Filter

Circuit Function and Advantages

The circuit in Figure 1 is a narrow-bandpass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.

The overall circuit bandwidth is 18 MHz with a passband flatness of 3 dB. With a 127 MHz analog input, the measured signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, so the IF input signal is positioned in the second Nyquist frequency zone between 102.5 MHz and 205 MHz.

Circuit Description

The circuit accepts a single-ended input and converts it to a differential signal using a wide bandwidth (3 GHz) Mini-Circuits TC2-1T 1:2 transformer. The ADL5565 6 GHz differential amplifier has a differential input impedance of 200 Ω when operating at a gain of 6 dB and 100 Ω when operating at a gain of 12 dB. It also provides a gain option of 15.5 dB.

The ADL5565 is an ideal driver for the AD9642 . The band-pass filter enables a fully differential architecture in the ADC, providing good high frequency common-mode rejection while minimizing second-order distortion products. The ADL5565 provides a gain of 6 dB or 12 dB, depending on the input connections. This circuit uses a gain of 12 dB to compensate for the insertion loss of the filter network and transformer (approximately 5.8 dB), resulting in a total signal gain of 5.5 dB.

Figure 1. 14-Bit, 250 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown). Gain, loss, and signal level measured at 127 MHz input frequency.

An input signal of 1.5 dBm produces a 1.75 V pp full-scale differential signal at the ADC input.

The anti-aliasing filter is a third-order Butterworth filter designed using a standard filter design program. The Butterworth filter was chosen because of its passband flatness. The third-order filter produces an ac noise bandwidth noise ratio of 1.05 and can be designed using a number of free filter programs such as Nuhertz Technologies Filter Free or Quite Universal Circuit Simulator (Qucs) Free Simulation.

For optimum performance, the ADL5565 should be loaded with a net differential load of 200 Ω. The 15 Ω series resistors isolate the filter capacitors from the amplifier outputs, and the 100 Ω resistors are in parallel with the downstream impedance, creating a net load impedance of 217 Ω when the 30 Ω series resistors are added.

The 5 Ω resistors in series with the ADC inputs isolate the internal switching transients from the filter and amplifier.

The 2.85 kΩ input impedance is determined from a spreadsheet that can be downloaded from the AD9642 web page. Simply use the shunt tracking mode value when the IF frequency of interest is centered. The spreadsheet gives both real and imaginary values.

A third-order Butterworth filter was designed with a source impedance (differential) of 200 Ω, a load impedance (differential) of 200 Ω, a center frequency of 127 MHz, and a 3 dB bandwidth of 20 MHz. The values ​​calculated by a standard filter design program are shown in Figure 1. Because a larger series inductor is required, the 1.59 μH inductor is reduced to 620 nH, and the 0.987 pF capacitor is scaled up to 2.53 pF, thus keeping the resonant frequency at 127 MHz unchanged and making the component values ​​more realistic.

Figure 2. Beginning design of a third-order differential Butterworth filter, ZS = 200 Ω, ZL = 200 Ω, FC = 127 MHz, BW = 20 MHz.

The value of the second shunt capacitor is subtracted from the 2.5 pF internal capacitance of the ADC, resulting in a value of 37.3 pF. In this circuit, the capacitor is placed close to the ADC to reduce/absorb charge kickback.

The values ​​chosen for the final filter passive components (after adjusting for actual circuit parasitics) are shown in Figure 1. Table 1 summarizes the measured performance of the system, with a 3 dB bandwidth of 18 MHz centered at 127 MHz. The total insertion loss of the network is approximately 5.8 dB. Figure 3 shows the frequency response; Figure 4 shows the SNR and SFDR performance.

Table 1. Measured performance of the circuit

Figure 3. Passband flatness performance vs. frequency

Figure 4. SNR/SFDR Performance vs. Frequency, Sampling Rate = 205 MSPS

Figure 5. General differential amplifier/ADC interface using a bandpass filter.

Filter and Interface Design Program

This section introduces a common approach to amplifier/ADC and bandpass filter interface design. To achieve the best performance (bandwidth, SNR, and SFDR), the amplifier and ADC impose certain design constraints on the general circuit.

1. The amplifier must be rated for the correct DC load as recommended in the data sheet for optimal performance.
2. The correct amount of series resistance must be used between the amplifier and the load of the filter. This is to prevent unwanted signal spikes within the passband.
3. The input of the ADC must be dropped with an external shunt resistor and the correct series resistance used to isolate the ADC from the filter. This series resistance will also reduce signal spikes.

The general circuit shown in Figure 5 is suitable for most high speed differential amplifier/ADC interfaces and serves as the basis for a bandpass filter. This design approach tends to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high speed ADCs and the relatively low impedance of the driving source (amplifier).

The basic design process is as follows:

1. Set the external ADC termination resistor, R _TADC , so that its parallel combination with R _{ADC is between 200 Ω and 400 Ω. 2. Select R KB} based on experience and/or ADC data sheet recommendations , typically between 5 Ω and 36 Ω. 3. Calculate the filter load impedance, Z _{AAFL ,} using the following equation : 2R _TADC || (R _ADC + 2R _KB )

4. Select the amplifier external series resistor, RR _A . If the amplifier differential output impedance is in the range of 100 Ω to 200 Ω, RA _should be less than 10 Ω. If the amplifier output impedance is 12 Ω or less, RA should be between 5 Ω and 36 Ω. 5. Select Z _AAFL so that the total load seen by the amplifier, Z _{AL ,} is best suited for the specific differential amplifier selected using the following equation:

Z _AL = 2RA ₊ Z _AAFL

6. Calculate the filter source impedance using the following formula:

Z _AAFS = Z _O + _2RA

7. Using a filter design program or spreadsheet, and using the source impedance Z _AAFS , load impedance Z _AAFL , filter type, bandwidth, and order, design the filter. The actual bandwidth used should be 10% higher than the required bandwidth of the application passband to ensure flatness over frequency.

After the above preliminary calculations, the following items of the circuit must be understood.

1. The value of C _AAF3 must be at least 10 pF, several times larger than C _{ADC . This minimizes the filter's sensitivity to fluctuations in C ADC} . 2. The ratio of Z _AAFL to Z _AAFS must not be higher than about 7, which keeps the filter within the limits of most filter tables and design programs. 3. The value of C _AAF1 must be at least 5 pF to minimize sensitivity to parasitic capacitance and component fluctuations. 4. The inductor L _AAF must be a reasonable value, at least a few nH. 5. C _AFF2 and L _AAF1 must be reasonable values. Sometimes circuit simulators will make these values ​​too low or too high. To make these values ​​more reasonable, just keep the same resonant frequency and compare these values ​​to better standard value components.

In some cases, the filter design program can provide more than one unique solution, especially for higher order filters. The solution with the most reasonable combination of component values ​​should always be selected. Also choose a configuration that ends with a shunt capacitor so that the shunt capacitor combines with the ADC input capacitance.

Circuit Optimization Techniques and Trade-offs

The parameters within this interface circuit are highly interactive; therefore, it is almost impossible to optimize all of the circuit's key specifications (bandwidth, bandwidth flatness, SNR, SFDR, and gain). However, by varying R _A and R _KB , the signal peaking that typically occurs within the bandwidth response can be minimized.

_{The value of RA} also affects the SNR performance. Larger values ​​tend to slightly improve SNR while reducing bandwidth peaking because higher signal levels are required to drive the ADC full scale.

_{The R KB} series resistor at the ADC input is chosen to minimize distortion caused by any residual charge injection (from the ADC internal sampling capacitor). Increasing this resistor also tends to reduce in-band signal peaking.

However, increasing R _KB increases signal attenuation, so the amplifier must drive a larger signal to fill the ADC's input range.

To optimize the center frequency, the passband characteristics, series capacitance, and CAAF2 _can be varied within a small range.

The ADC input termination resistor, RTADC _, is typically chosen so that the net ADC input impedance is between 200 Ω and 400 Ω, a typical characteristic load value for most amplifiers. Choosing a value that is too high or too low can adversely affect the linearity of the amplifier.

The trade-offs between the above factors can be difficult. In this design, each parameter was given equal weight; therefore, the values ​​chosen represent the interface performance for all design features. In some designs, different values ​​may be chosen to optimize SFDR, SNR, or input drive level, depending on system requirements.

The SFDR performance of this design depends on two factors: the amplifier and the ADC interface component values, as shown in Figure 1.

Note that the signals in this design are ac coupled with 0.1 μF capacitors to block the common-mode voltage between the amplifier, its termination resistors, and the ADC inputs. For more information on common-mode voltage, refer to the AD9642 data sheet.

Passive Components and PCB Parasitic Considerations

The performance of this or any high speed circuit is highly dependent on proper printed circuit board (PCB) layout. This includes, but is not limited to, power supply bypassing, controlled impedance lines (where necessary), component placement, signal routing, and power and ground planes. See Tutorials MT-031 and MT-101 for more detailed information on high speed ADC and amplifier PCB layout. Also, refer to CN-0227 and CN-0238 .

For the passive components within the filter, low parasitic surface mount capacitors, inductors, and resistors were used. The inductors selected were from the Coilcraft 0603CS series. The surface mount capacitors used in the filter were 5%, C0G, 0402 type to ensure stability and accuracy.

Complete documentation for the system can be found in the CN-0279 Design Support Package

Common changes

The AD9643 is a dual-channel version of the AD9642.

For lower power and bandwidth, the ADA4950-1 and/or ADL5561 / ADL5562 can also be used . These parts are pin compatible with the single-channel parts listed previously.

Circuit Evaluation and Testing

This circuit uses a modified AD9642-250EBZ circuit board and the HSC-ADC-EVALCZ FPGA-based data capture board. The two boards have mating high-speed connectors that allow for quick setup and evaluation of the circuit performance. The modified AD9642-250EBZ board includes the evaluation circuit described in this note, and the HSC-ADC-EVALCZ data capture board is used with the VisualAnalog® evaluation software, along with the SPI controller software to properly control the ADC and capture data. The schematic, BOM, and layout for the AD9642-250EBZ board are provided in User Guide UG-386 . The readme.txt in the CN-0279 Design Support Package describes the modifications made to the standard AD9642-250EBZ board. Application Note AN-835 details how to set up the hardware and software to run the tests described in this circuit note.