Enhanced Parallel Port (EPP) is an extended shift register output interface.-EEWORLD

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【Abstract】 Based on the characteristics of EPP protocol, a shift register output interface is developed using complex programmable logic device (CPLD). The Verilog HDL description of EPP protocol and interface is introduced.
Keywords: Enhanced Parallel Port (EPP), shift register output, CPLD, Verilog HDL

1 Introduction

As the number of ISA bus slots in desktop computers gradually decreases or even disappears, parallel ports are increasingly used for data transmission in microcomputer control systems. The Enhanced Parallel Port (EPP) is not only compatible with the traditional standard parallel port (SPP), but also has a transmission rate of 500k~2Mbyte/s (equivalent to the transmission rate of the ISA bus). In particular, EPP provides hardware handshake signals, which facilitates software and hardware design. Therefore, the application of EPP in industrial control is becoming more and more extensive.
Some dot matrix control devices such as thermal print heads and LED display drivers generally use shift registers to receive data due to the large number of control points. If a parallel I/O port is used to generate shift register output data and synchronization pulses, multiple I/O read and write cycles are usually required. Here we introduce a solution to use the EPP parallel port to expand the shift register output interface, which can complete the output of one byte in one I/O read and write cycle to achieve the effect of high-speed transmission.

2 Introduction to the EPP protocol

The EPP protocol is a bidirectional transmission parallel interface specified in IEEE1284, which maintains compatibility with the standard parallel port (SPP). Table 1 shows the pin definitions and functions of SPP and EPP.

Among them, pins 12, 13, and 15 are undefined in EPP, and users can use them flexibly as needed.
The EPP register occupies 8 adjacent I/O address spaces. The base address +0 to +2 is the same as SPP, which are the data register, status register, and control register of SPP respectively. I/O operations on them will not generate EPP read and write cycles. Base address +3 is the EPP address port, and base address +4 is the EPP data port. I/O operations on them can generate EPP address or data read and write cycles.

The EPP protocol specifies four data transfer cycles: write data cycle, read data cycle, write address cycle, and read address cycle. Figure 1 is the timing of the EPP write data cycle. Wait is a hardware handshake signal. After the ISA read and write cycle starts, if Wait is low, it means that the EPP write data cycle can start. At this time, Data Strobe (or Address Strobe) becomes low, entering the EPP write data cycle (time 3), and then waiting for Wait to become high. When Wait becomes high, it means that the EPP read and write cycle can be ended. Data Strobe (or Address Strobe) becomes high, ending the EPP write data cycle (time 5), and then the ISA read and write cycle ends. It can be seen that the transmission of a data or address is completed within an ISA cycle, so the ISA transmission rate can be achieved. In the EPP cycle, if Wait is delayed to become high, the EPP cycle can be extended. This allows the computer and peripherals to match in speed. To prevent the system from locking when there is no peripheral, the EPP controller is equipped with a watchdog. Usually, 10μs after the start of the ISA cycle, if Wait does not respond, the controller will end the I/O cycle and generate an EPP timeout error, and bit0 (timeout flag) of the status register will be set.

3 Implementation of the shift register output interface

The EPP parallel port extended shift register output interface proposed in this paper mainly uses the Wait handshake signal. During the shift register shifting process, the Wait signal is kept low to prevent the EPP cycle from ending, so that the shift output is completed within one EPP cycle. In addition, a counter is used to control the shift register shifting to ensure that only 8 shift actions occur within one EPP cycle to prevent data errors.
The hardware circuit is implemented using Altera's complex programmable logic device (CPLD). Its structure is described in Verilog HDL language. Among them, nCs is the chip select signal, which is generated by address decoding (the description of address output and decoding is omitted), Clk is the external clock source, and DataOut and ClkOut are output data and output synchronization pulses respectively. To prevent the system from timeout, Clk should have a higher frequency, about 10 MHz. The Verilog HDL description of the interface is as follows:

4 Conclusion

Using EPP parallel port to expand the shift register output interface makes full use of EPP handshake signals. Therefore, there is no need to query the status of the shift register during software design. Only the base address + 4 port needs to be written to complete the output of one byte of the shift register, which simplifies software programming and achieves a high transmission rate (transmission rate can reach 8Mbit/s). Taking this as an example, multiple switch channel interfaces can also be expanded.

References

1 Institute of Electrical and Electronics． IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers． IEEEStd 1284，2000
2 Song Wanjie et al． CPLD Technology and Its Applications． Xi'an: Xi'an University of Electronic Science and Technology Press，1999
3 J． Bhasker． Verilog HDL Hardware Description Language． Beijing: Machinery Industry Press，2000

Reference address：Enhanced Parallel Port (EPP) is an extended shift register output interface.

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