Points to note in EMC circuit design

When considering EMI control, design engineers and PCB board-level design engineers should first consider the selection of IC chips. Certain characteristics of integrated circuits such as package type, bias voltage and chip process technology (such as CMoS, ECI, Knife 1) have a great impact on electromagnetic interference.

1. Source of integrated circuit EMl

The main sources of EMI for integrated circuits in PCBs are: EMI caused by the square wave signal frequency generated at the output end during the conversion of digital integrated circuits from logic high to logic low or from logic low to logic high.

2 Signal voltage and signal current Electric and magnetic fields Capacitance and inductance of the chip itself, etc. The square wave generated at the output of the integrated circuit chip contains sinusoidal harmonic components with a wide frequency range. These sinusoidal harmonic components constitute the EMI frequency components that engineers are concerned about. The highest EMI frequency is also called the EMI emission bandwidth, which is a function of the signal rise time (not the signal frequency).

The formula for calculating EMI emission bandwidth is: f=0.35/Tr

Where, κ is the frequency in GHz, and κ is the signal rise time or fall time in ns.

From the above formula, we can see that if the switching frequency of the circuit is 50MHz, and the rise time of the integrated circuit chip used is 1ns, then the highest EMI emission frequency of the circuit will reach 350MHz, which is much larger than the switching frequency of the circuit. If the rise time of the integrated circuit chip is 5ns, then the highest EMI emission frequency of the circuit will be as high as 700MHz.

Each voltage value in the circuit corresponds to a certain current, and each current also has a corresponding voltage. When the output of the IC changes from logic high to logic low or from logic low to logic high, these signal voltages and signal currents will generate electric and magnetic fields, and the highest frequency of these electric and magnetic fields is the emission bandwidth. The intensity of the electric and magnetic fields and the percentage of external radiation are not only a function of the signal rise time, but also depend on the control of the capacitance and inductance on the signal channel between the signal source and the load point. Therefore, the signal source is located inside the sink of the PCB board, and the load is located inside other ICs, which may or may not be on the PCB. In order to effectively control EMI, it is necessary not only to pay attention to the capacitance and inductance of the sink itself, but also to pay attention to the capacitance and inductance on the PCB.

When the signal voltage and the signal loop are not tightly coupled, the capacitance of the circuit will decrease, and the suppression of the electric field will be weakened, which will increase EMI. The same situation exists for the current in the circuit. If the current and the return path are not well coupled, the inductance of the loop will increase, thereby enhancing the magnetic field and ultimately increasing EMI. This fully demonstrates that poor control of the electric field usually leads to poor suppression of the magnetic field. The measures used to control the electromagnetic field in the circuit board are roughly similar to those used to suppress the electromagnetic field in the IC package. Just as with the PCB design, the IC package design will greatly affect EMI.

A considerable portion of electromagnetic radiation in the circuit is caused by voltage transients in the power bus. When the output stage of the sink jumps and drives the connected PCB line to logic "high", the sink chip will absorb current from the power supply to provide the energy needed by the output stage. For the ultra-high frequency current generated by the continuous conversion of the IC, the power bus and the decoupling network on the PCB end at the output stage of the sink. If the signal rise time of the output stage is 1.0ns, then the IC must absorb enough current from the power supply within such a short time of 1.0ns to drive the transmission line on the PCB. The transient change of voltage on the power bus depends on the inductance, the absorbed current and the transmission time of the current on the power line path. The voltage transient is defined by the following formula:

Where L is the value of the inductance on the current transmission path; dj represents the change in current during the signal rise time interval; and dz represents the change in the current transmission time (signal rise time).

Since the IC pins and internal circuits are part of the power bus, and the absorption current and output signal startup time also depend on the process technology of the sink to a certain extent, choosing a suitable sink can largely control the three factors mentioned in the above formula.

The role of packaging features in EMI control

IC packages usually include a silicon-based chip, a small internal PCB, and pads. The silicon-based chip is mounted on a small 64-inch PCB, and the connection between the silicon-based chip and the pad is achieved through binding wires. In some packages, a direct connection to the small PCB can also be achieved to connect the signal and power on the silicon-based chip to the corresponding pins on the package, thus realizing the external extension of the signal and power nodes on the silicon-based chip. Therefore, the transmission path of the power supply and signal of the package includes the silicon-based chip, the connection between the small PCB, the PCB routing, and the input and output pins of the package. The control of capacitance and inductance (corresponding to electric field and magnetic field) depends largely on the design of the entire transmission path. Certain design features will directly affect the capacitance and inductance of the entire IC chip package.

Let's first look at the connection method between the silicon-based chip and the internal small circuit board. Many integrated chips use bonding wires to connect the silicon-based chip to the internal small circuit board. This is an extremely thin 6t wire between the silicon-based chip and the internal small circuit board. This technology is widely used because the thermal expansion coefficient (CU) of the silicon-based chip and the internal small circuit board is similar. The chip itself is a silicon-based device, and its thermal expansion coefficient is quite different from the thermal expansion coefficient of typical PCB materials (such as epoxy resin). For example, if the electrical connection point of the silicon-based chip is directly installed on the internal small PCB, then after a relatively short period of time, the change in temperature inside the IC package causes thermal expansion and contraction, and this type of connection will fail due to breakage. The bonding wire is a lead method that adapts to this special environment. It can withstand bending deformation under large loads and is not easy to break.

The problem with wirebinding is that the increase in the current loop area of ​​each signal or power line will lead to an increase in inductance value. A good design to achieve a lower inductance value is to achieve a direct connection between the silicon-based chip and the internal PCB, that is, the connection point of the silicon-based chip is directly connected to the pad of the PCB. This requires the selection of a special PCB board material, which should have an extremely low thermal expansion coefficient. The selection of this material will increase the overall cost of the chip, so chips using this process technology are not common, but as long as such an IC that directly connects the silicon-based chip to the carrier PCB exists and is feasible in the design solution, then using such an IC device is a better choice.

Generally speaking, in the design of integrated circuit packages, reducing inductance and increasing capacitance between the signal and the corresponding loop or between the power supply and the ground are the primary considerations in the process of selecting integrated circuit chips. For example, compared with surface mounting with small pitch and surface mounting with large pitch, the chip packaged with surface mounting technology with small pitch should be given priority, and both types of surface mounting technology packaged IC chips are better than through-hole lead type packages. BGA packaged chips have the lowest lead inductance compared to any commonly used package type. From the perspective of capacitance and inductance control, small packages and finer pitches usually always represent improved performance.

An important feature of the lead structure design is the pin allocation. Since the inductance and capacitance values ​​depend on the proximity between the signal or power supply and the return path, it is necessary to consider enough return paths.

Power pins and ground pins should be allocated in pairs, each power pin should have a corresponding ground pin adjacent to it, and multiple power pins and ground pin pairs should be allocated in this lead structure. Both of these features will greatly reduce the loop inductance between power and ground, help reduce voltage transients on the power bus, and thus reduce EAdI. Due to customary reasons, many chips on the market now do not fully follow the above design rules, but IC designers and manufacturers deeply understand the advantages of this design method, so IC manufacturers pay more attention to power connection when designing and releasing new IC chips.

Ideally, each signal pin should be assigned an adjacent signal return pin (such as a ground pin). This is not the case in reality, and many IC manufacturers use other compromise methods. In BGA packaging, an effective design method is to set a signal return pin in the center of each group of eight signal pins. In this pin arrangement, each signal is only one pin away from the signal return path. However, for ICs in quad flat package (QFP) or other gull-wing packaging forms, it is unrealistic to place a signal return path in the center of the signal group. Even so, a signal return pin must be placed every 4 to 6 pins. It should be noted that different sink process technologies may use different signal return voltages. Some ICs use ground pins (such as TIL devices) as signal return paths, while some ICs use power pins (such as most ECI' devices) as signal return paths, and some ICs use both power pins and ground pins (such as most CMoS devices) as signal return paths. Therefore, design engineers must be familiar with the IC chip logic series used in the design and understand their related working conditions.

Reasonable distribution of power and ground pins in IC chips can not only reduce EMI, but also greatly improve the ground bounce effect. When the device driving the transmission line tries to pull the transmission line to a logic low, the ground bounce still maintains the transmission line above the logic low closed value level, and the ground bounce may cause the circuit to fail or malfunction.

Another important issue that needs to be paid attention to in IC packaging is the PCB design inside the chip. The internal PCB is usually the largest component of the IC package. If the capacitance and inductance can be strictly controlled during the internal PCB design, the overall EMI performance of the system will be greatly improved. If this is a two-layer PCB board, at least one side of the PCB board is required to be a continuous ground plane layer, and the other side of the PCB board is the wiring layer for power and signals. The more ideal situation is a four-layer PCB board, with the two middle layers being the power and ground plane layers, and the two outer layers being the wiring layers for signals. Since the PCB inside the package is usually very thin, the design of the four-layer board structure will lead to two high-capacitance, low-inductance wiring layers, which is particularly suitable for power distribution and input and output signals that need to be strictly controlled in and out of the package. The low-impedance plane layer can greatly reduce the voltage transients of the power bus, thereby greatly improving the EMI performance.