Discrete comparator/DAC combination solves data acquisition problems

The following discussion demonstrates an alternative that is often overlooked in existing A/D converter applications: A/D conversion can be more easily accomplished using discrete comparators and D/A converters under certain conditions. This alternative often uses a different test methodology, but offers advantages such as lower cost, higher speed, greater flexibility, and lower power consumption.

Transient Voltage Analysis

The "brute force" technique for capturing fast amplitude change events (transients) is to simply quantize them using a high-speed ADC and RAM supported by the processor (Figure 1). Single-trigger events may necessitate this approach because the details of the transient need to be captured. However, if the transients are repetitive, a DAC/comparator approach can be used to measure their peak amplitude and other characteristics (Figure 2).

One input pin of the comparator has a DAC setting the decision level, and the transient signal is applied to the other input. The peak transient amplitude can be determined by adjusting the DAC output. When the threshold is exceeded, a digital latch is used to capture the comparator output response. Only the comparator input needs to support the transient bandwidth, and the arbitrarily long DAC output settling time does not affect the measurement accuracy. In this way, a low-cost DAC and comparator can replace an expensive ADC in the analog domain.

Figure 1. Using the “brute force” method for transient analysis, the ADC circuit consumes a lot of power and is expensive.

Figure 2 If repeated amplitude measurements are acceptable for the application in Figure 1, replacing the ADC with a DAC/comparator combination can save power and reduce cost.

It is important to note that tolerances must be considered when monitoring analog voltages. Many self-diagnostic devices monitor system voltages, temperatures, and other analog quantities, with tolerances set in software. However, if this comparison is implemented by a comparator and the set value is provided by a DAC, this can reduce the processor load because only one bit needs to be read to indicate an out-of-limit condition.

This technique (analog domain comparison) has the same accuracy as the ADC technique (digital domain comparison). For one set point, this can be achieved through a simple comparison. Why do we need to quantize the entire value? One case that must be mentioned is: if there are several set points to compare with, such as the alarm upper/lower limit and shutdown lower/upper limit levels, the ADC can be selected. Otherwise, 4 DACs and 4 comparators are required.

Building a simple ADC from a DAC

Portable instruments are limited by cost and size, and in some cases, a DAC can be used to perform the A/D conversion function. For example, cell phones and medical electronics often use DACs to adjust the LCD contrast voltage (Figure 3). Sometimes, temperature or battery voltage can be monitored by simply adding a comparator and switch (as described above). The existing DAC can then perform two tasks, turning off the display while the DAC performs the analog-to-digital conversion. As another alternative, a simple sample/hold circuit consisting of an analog switch and capacitor (Figure 4) can maintain the LCD contrast voltage during the A/D conversion.

Figure 3 This circuit is commonly found in portable instruments

Figure 4 adds two comparators to Figure 3, and uses the DAC to implement the ADC function, saving costs.

Another approach is to replace the existing single DAC with a low-cost dual DAC. One of the dual DACs is used to generate the LCD contrast voltage, and the other is used to form the ADC. Whether single or dual, the DAC and comparator support fast, simple procedures for driving the DAC, and sampling the comparator to achieve successive approximation.

Design considerations

The combination of DAC and comparator is very simple. The signal acts on the non-inverting input of the comparator, and the digital programmable threshold provided by the DAC acts on the inverting input. As long as the signal is greater than the threshold value, the comparator will generate a logic high output. However, several aspects must be paid attention to when using it:

To ensure accurate threshold levels, the DC output impedance of the DAC should be small, taking into account the input bias current of the comparator and the ratio network. This is especially important in ultra-low power circuits, where the output impedance of the DAC may be as high as 10kΩ.

Another requirement for DACs is low AC output impedance. Otherwise, the slew rate of the high-speed digital signal at the comparator output will be coupled through the wiring parasitic capacitance, which will produce input transient changes, leading to self-excitation and reduced accuracy. If a certain settling time can be sacrificed, a bypass capacitor can be added to the comparator input to reduce the AC output impedance of the DAC. The large capacitive load of the DAC output amplifier can cause instability or oscillation, but this problem can be corrected by connecting a resistor in series with the DAC output.

The main problem with comparators is hysteresis. Most comparator circuits have hysteresis to prevent noise and oscillation, but hysteresis must be used with caution—it causes the threshold to change with the output. If the system can compensate for the hysteresis affected by the output state, this configuration is acceptable; otherwise, hysteresis should be avoided.

If the comparator used has internal hysteresis and cannot be disabled, the negative effects can be eliminated by ensuring that the DAC output always approaches the comparator threshold in the same direction. This can be easily achieved by setting the DAC to zero after each bit of the test; for example, by adding a line after the pseudocode listed at the end of this article.

Alternatively, the hysteresis can be eliminated by adding a small capacitor feedback, which speeds up the comparator's transition through the linear region of operation. Alternatively, an output flip-flop or latch can be added to capture the comparator output state at a given moment.

Today's comparators are well suited to handling slew-rate limited input signals. For example, the MAX913 and MAX912 from Maxim are particularly effective in this regard because they are stable in their linear region of operation. Figure 5 illustrates the performance of the MAX913 in a high-speed, 12-bit application. The circuit in Figure 6 (an ultra-low-power 8-bit converter) can be shut down to save energy when not in use.

Figure 5 This high-speed, 12-bit amplitude collector can handle slow input voltages because the comparator remains stable in its linear region of operation.

Figure 6 This low-voltage, 8-bit data-collector alternative to an ADC offers several advantages: low cost, low power consumption, and the ability to shut down during sampling intervals.

DAC/Comparator Combination ICs

Maxim offers three single-chip devices that greatly simplify design by combining a comparator and a DAC. Each device is well suited for this and many other applications.

For example, the MAX516 is a 4-channel device with submicrosecond speeds that is well suited for a variety of moderate-speed, multichannel applications (Figure 7a).

The MAX910 is a single-channel, high-speed, TTL-output DAC/comparator with an 8ns propagation delay (Figure 7b). A similar device (MAX911) is even faster—ECL complementary outputs with a 4ns propagation delay.

Figure 7. Maxim 8-bit DAC/comparator ICs include the 4-channel MAX516 (a), the high-speed, TTL-compatible MAX910 (b), and the ECL-compatible MAX911 (not shown).

Successive approximation

Successive approximation is easily illustrated using a scale and a series of binary weights (relative values ​​of 1, 2, 4, 8, 16, etc.) used to determine the weight of an object. The quickest way to determine an unknown weight (successive approximation) is to first compare the unknown weight to the largest weight. Depending on the scale's instructions, either remove that weight or add the next largest weight, and so on to the smallest weight. The weight of the object is the sum of the weights remaining on the scale pan.

In a successive approximation ADC, the bits of an internal DAC emulate a series of binary weights, and the comparator output emulates a scale indication. The logic that drives the weight bit processing resides in the packaged ADC's successive approximation register (SAR) or in a processor software subroutine that controls the DAC/comparator circuitry and can be implemented in less than 20 lines of code (Table 1).