TTL integrated logic gate circuit

3.3 TTL integrated logic gate circuit
3.3.1
TTL NAND gate 1. Working principle of TTL NAND gate
1. Circuit structure
2. Working principle

2. Working speed
1. Use anti-saturation transistor
2. Use active discharge circuit

3. Voltage transfer characteristics and noise tolerance
1. Voltage transfer characteristics
2. Closed gate level, open gate level and threshold voltage
3. Noise tolerance

4. Input load characteristics

5. Output load characteristics
1. Output low level load characteristics
2. Output high level load characteristics

6. Transmission delay time

3.3.2 Low power Schottky series

Homework: P36 2.4 2.5

3.3 TTL integrated logic gate circuit
3.3.1 TTL NAND gate
You only need to understand the principle of the internal circuit, and you need to master the external characteristics.
1. The working principle of TTL NAND gate using PowerPoint
1. Circuit structure

2. Working Principle①
Input has low level 0.3V: K point potential is 1V V1 is on V2V5 is off, V3V4 is on. (F is 3.6V high level.)
② Input is all high level 3V then K point potential is 3.7V Under
the clamping of three PN junctions VK=2.1v V1 collector junction is forward biased emitter junction is reverse biased.
R1 is in inverted working state (B reverse)
R1 V5-saturated M point potential 1V
then V3——slightly on V4——off (then F=0.3V low level)
By ①,②

1. Use anti-saturation transistors
The deeper the transistor saturation, the slower its working speed. To increase the working speed of the circuit, it is necessary to try to make the transistor work in a shallow saturation state. For this purpose, anti-saturation transistors are needed.
2. Use active discharge circuit
After V5 is turned on, V6 is turned on next, which shunts part of the base current of V5, making V5 work in a shallow saturation state, which is also conducive to shortening the time for V5 to switch from on to off.
When V2 switches from on to off, since V6 is still in the on state, it provides a low-resistance path for the discharge of the stored charge in the base region of V5, accelerates the cutoff of V5, and thus shortens the turn-off time.

3. Voltage transfer characteristics and noise tolerance
1. Voltage transfer characteristics

2. Gate-off level, gate-on level and threshold voltage
(1) Gate-off level
When the output is guaranteed to be the standard high level USH (usually USH＝3V), the maximum value of the input low level is called the gate-off level, represented by UOFF. From the above figure, we can get UOFF≈1.0V. Obviously, only when the input uI＜UOFF, the NAND gate is closed and the output is high level.
(2) Gate-on level
When the output is guaranteed to be the standard low level USL (usually USL＝0.3V), the minimum value of the input high level is called the gate-on level, represented by UON. From the above figure, we can get UON≈1.2V. Obviously, only when uI＞UON, the NAND gate is turned on and the output is low level.
(3) Threshold voltage
The input voltage corresponding to the midpoint of the voltage transfer characteristic inflection zone is called the threshold voltage, also known as the threshold level.

3. Noise tolerance and interference capability
VNL (low level noise tolerance) = VOFF-VIL
VNL (high level noise tolerance) = VIH-VON

4. Input load characteristics

5. Output load characteristics
The characteristic curve of output voltage U0 changing with load current i0 is called output load characteristics.

3.3.2 Low power Schottky series

1. Low power consumption
In order to reduce power consumption, the resistance of each resistor in the circuit is greatly increased. At the same time, R5 is changed from grounding to connecting to the output terminal, which reduces the power consumption on R5 when V3 is turned on, thereby reducing the power consumption of the entire circuit. Its power consumption is about 2mW, which is only 1/10 of the CT74S series.

2. High operating speed
In order to improve the operating speed, the circuit adopts the following measures:
(1) The circuit adopts an anti-saturation transistor and an active discharge circuit composed of V6, RB and RC.
(2) The multi-emitter transistor V1 of the input stage is replaced by a Schottky barrier diode SBD without charge storage effect. In this way, when the input signal changes, the transient response is fast, which improves the operating speed.
(3) Two SBDs, VD4 and VD5, are connected between the output stage and the intermediate stage.