Data Selectors and Allocators

2. Logical function analysis

The following analysis takes a data selector in Figure 6.5.2 in the textbook as an example.

(1) The opening and closing of the first-stage transmission gates 1TG1~1TG4 are controlled by A0.
When A0=0, 1TG1 and 1TG3 are opened, and 1TG2 and 1TG4 are closed; when A0=1, 1TG1 and 1TG3 are closed, and 1TG2 and 1TG4 are opened.
(2) The opening and closing of the second-stage transmission gates 1TG5 and 1TG6 are controlled by A1.
When A1=0, 1TG5 is opened, and 1TG6 is closed; when A1=1, 1TG5 is closed, and 1TG6 is opened.
In this way, after the value of A1A0 is determined, and when it takes 1=0, there is a corresponding data output in the input data 1D0~1D3.

3. Truth table

Table 6.5.2 Truth table of dual 4-to-1 data selector CC14539

4. Output logic function

2. 8-to-1 data selector

MSI device TTL 8: Select 1 data selector CT74LS151
1. Logic function diagram

2. Truth table

Table 6.5.3 Truth table of data selector CT74LS151

3. Output logic function

3. Implementing Combinational Logic Functions with Data Selectors

Implementation principle: The data selector is a minimum term outputter of a logical function:

Any logic function of n-bit variables can be transformed into the standard form of the sum of minimum terms

, Ki's value is 0 or 1, so the data selector can be used to easily implement the logic function.
Method: ⑴ Expression comparison method, compare and . ⑵ Karnaugh map comparison method.
1. When the number of variables of the logic function is the same as the number of address input variables of the data selector, the data selector can be used directly to implement the logic function.

[Example 6.5.1] Try to use the data selector to implement the logic function
Y = AB + AC + BC
Solution: This problem can be solved by algebraic method and Karnaugh map method.
Algebraic method
(1) Select a data selector. Since there are three variables A, B, and C in the logic function Y, an 8-to-1 data selector can be selected. Now CT74LS151 is selected.
(2) Write the standard AND-OR expression of the logic function. The standard AND-OR expression of the logic function Y is

(3) Compare the corresponding relationship between the minimum terms in the two equations Y and Y'. Assume Y = Y', A = A2, B = A1, C = A0. When Y' contains the minimum term in Y, the data is 1, and when it does not contain the minimum term in Y, the data is 0. Thus,

(4) Draw a connection diagram. Based on the above formula, we can draw the connection diagram shown in Figure 6.5.4.

Karnaugh Map Method
(1) Write the standard AND-OR expression of the logic function Y as

(2) Draw the Karnaugh map of Y and the 8-to-1 data selector output logic function Y′. The Karnaugh maps of Y and Y′ are shown in Figure 6.5.5.

(3) Compare the Karnaugh maps of logic functions Y′ and Y. Let Y = Y′, A = A2, B = A1, C = A0, and compare the two Karnaugh maps in Figure 6.5.5 (a) and (b) to obtain

Figure 6.5.5 [Example 6.5.1] Karnaugh map
(a) Karnaugh map of Y; (b) Karnaugh map of

(4) Draw a connection diagram. Based on the above formula, we can draw the connection diagram of Figure 6.5.4.

2. When the number of variables of the logic function is greater than the number of address input variables of the data selector, the redundant variables should be separated and the remaining variables should be added to the address input terminals of the data selector in order.

[Example 6.5.2] Use dual 4-to-1 data selector CC14539 and NOT gate to form a one-bit full adder.

Solution: (1) Set variables and list the truth table.
Assume that the binary numbers are added at the i-th position
. Input variables: addend Ai, addend Bi, carry number from the lower position Ci-1
Output logic function: sum of the current position Si, carry number to the adjacent higher position is Ci.
Its truth table is shown in Table 6.5.4.

(4) Compare the output logic function of the full adder with the output logic function of the data selector. Assume Si = 1Y, Ai = A1, Bi = A0, then

(5) Draw a connection diagram.

Figure 6.5.6 Connection diagram of [Example 6.5.2]

From the above question, we can see that when the number of variables in the logic function is greater than the input address codes A1 and A0 of the data selector, then D3~D0 can be regarded as the third (input) variable, used to represent the variables separated from the logic function.

6.5.2 Data Allocator
Data allocation is the inverse process of data selection.

A circuit that distributes one data path to a specified output channel according to the requirements of the address signal is called a data distributor.

What is the logical function of the 3-line to 8-line MSI decoder?
If the enable terminal of the decoder is used as the data input terminal and the binary code input terminal is used as the address signal input terminal, the decoder becomes a data distributor.

An 8-way data distributor consisting of a 3-line to 8-line decoder CT74LS138.