Synchronous counter

Synchronous counter
I. Synchronous binary counter
1. Synchronous binary adder counter
JK flip-flop composed of 4-bit synchronous binary adder counter
Working principle introduction.
2. Synchronous binary subtraction counter
Design idea:
3. Integrated synchronous binary counter CT74LS161
logic function diagram.
Function table.
4. Use feedback setting method to obtain N-base counter
⑴ Counter setting function
⑵ Use feedback setting method to obtain N-base counter
Steps:
① Write the binary code of the counter state.
② Write the feedback reset function.
③ Draw a connection diagram.
[Example 7.3.2] Try to use CT74LS161 to form a decimal counter
[Example 7.3.3] Try to use CT74LS161 to form a decimal counter.
5. Synchronous binary adder/subtractor
II. Synchronous decimal adder counter
III. Integrated synchronous counter
1. Integrated decimal synchronous adder counter CT74LS160
2. Integrated decimal synchronous add/subtract counter CT74LS190
7.3.3B Using counter cascade to obtain large-capacity synchronous N-base counter
I. Cascade
method Method for implementing synchronous counter:
two CT74LS160s are cascaded into a 100-base synchronous adder counter.
II. Feedback zeroing method
Two 4-bit binary adder counters CT74LS161 are cascaded into a 50-base counter.
Modern teaching methods and means:
Use DLCCAI or EWB to demonstrate the logical functions of 74LS161, 74LS160, and 74LS190

7.3.2 Synchronous Counter
1. Synchronous Binary Counter

1. Synchronous Binary Adder Counter
Depending on the students’ level, sometimes we can also discuss the design ideas of synchronous binary counters from a design perspective.
[In a synchronous counter, the CP terminals of all triggers are connected, and each trigger edge of CP will update the status of all triggers. Therefore, T′ triggers cannot be used.
The input terminal of the trigger should be controlled, that is, the trigger is connected to a T trigger.
Only when the low bit carries to the high bit (that is, add 1 when all low bits are 1), the T of the high bit trigger is set to 1, the trigger flips, and the count increases by 1.]

The 4-bit synchronous binary adder counter composed of JK flip-flops (see Figure 7.3.7 in the textbook)
is triggered by the falling edge. The following is an analysis of its working principle. (Consolidate the analysis method of the synchronous counter and briefly introduce the ideas. Students can learn the details by themselves. No need to write on the blackboard)

(2) List the state transition truth table.
AND/OR formula (state equation) → truth table (state transition truth table).
The current state is regarded as the input variable and the next state is regarded as the output function.

(3) Logical functions: Hexadecimal counter.

2. Synchronous Binary Down Counter

Design idea:
[In a synchronous counter, the CP terminals of all triggers are connected, and each trigger edge of CP will update the status of all triggers. Therefore, the T' trigger cannot be used.
The input terminal of the trigger should be controlled, that is, the trigger is connected to a T trigger.
Only when the low bit borrows from the high bit (that is, when the low bit is all 0, it is subtracted by 1), the T of the high bit trigger is set to 1, the trigger flips, and the count is reduced by 1. ]
To this end, as long as the output of the binary adder counter is changed from the Q terminal to the Q terminal, it becomes a synchronous binary subtraction counter.

3. Integrated synchronous binary counter CT74LS161

Main function analysis: (See the function table analysis, no need to write on the blackboard.)

4. Using the feedback setting method to obtain an N-base counter

⑴ Counter setting function
The counting start data should be pre-set into the counter.
There are two ways to set the integrated counter: asynchronous and synchronous.
① Asynchronous setting: It has nothing to do with the clock pulse CP. As long as the setting signal appears at the asynchronous setting control end, the parallel data will be set immediately.
② Synchronous setting: After the input end obtains the setting signal, it only creates conditions for setting. Another counting pulse CP needs to be input before the counter can set the preset number.
⑵ Using the feedback setting method to obtain an N-base counter
S0, S1, S2…, SN are used to represent the state of the counter when 0, 1, 2,…, N counting pulses CP are input. The
counting working state of the N-base counter should be N: S0, S1, S2…, SN-1.
For asynchronous setting: After the Nth counting pulse CP is input, a valid setting signal is generated by the state through the control circuit and sent to the asynchronous setting end, so that the counter returns to the initial preset state, that is, the N-base counting is realized.
For synchronous setting: when the N-1th counting pulse CP is input, a valid setting signal is generated by using the state and sent to the synchronous setting control terminal. When the Nth counting pulse CP is input, the counter returns to the initial preset number state, thereby realizing N-base counting.

Class discussion: To realize N-based counting, does the state appear when setting the number asynchronously?

Steps:
① Write the binary code of the counter state.
When using the asynchronous setting input terminal to obtain the N-based counter, write the corresponding binary code;
when using the synchronous setting terminal to obtain the N-based counter, write the corresponding binary code.
② Write the feedback reset function.
Write the logical expression of the setting terminal according to SN or SN-1.
③ Draw the connection diagram. Draw the connection diagram mainly based on the feedback setting function.

[Example 7.3.2] Try to use CT74LS161 to form a decimal counter
Solution: CT74LS161 implements hexadecimal, and its synchronous set control terminal can be used to implement decimal counting.
The first solution: Assume that counting starts from the state Q3Q2Q1Q0=0000, and take D3D2D1D0=0000.
The N-base counter obtained by using the set control terminal generally starts counting from 0.
(1) Write the binary code of SN-1 as

SN-1＝S10-1＝S9＝1001
(2) Write the feedback reset (set) function. Since the counter starts counting from 0, the feedback reset function
(7.3.4) should be written
. (3) Draw a connection diagram. Draw the connection diagram of the decimal counter according to the above formula and the setting requirements, as shown in Figure 7.3.9 (a).

The second solution: use the last 10 states 0110-1111, take D3D2D1D0=0110,

The feedback set signal is obtained from the carry output terminal CO.
Discussion: Why?
Take the state S15 = 1111, at this time CO = 1, through the NOT gate, it can replace the NAND gate.
The circuit is shown in Figure 7.3.9 (b).

[Example 7.3.3] Try to use CT74LS161 to construct a binary counter.
Solution: Assume that the count starts from the state of Q3Q2Q1Q0=0000.

(1) Use the asynchronous reset control terminal to achieve
① Write the binary code of S12 S12=1100
② Write the feedback reset function
(7.3.5)
③ Draw a connection diagram. As shown in Figure 7.3.10(a)

(2) Using the synchronous reset control terminal to achieve
Take D3D2D1D0 = 0000.
① Write the binary code of SN-1
S12-1 = S11 = 1011
② Write the feedback reset function
(7.3.6)
③ Draw a connection diagram. Draw a connection diagram based on the expression, as shown in Figure 7.3.10 (b).

5. Synchronous binary up/down counter

Review: Binary counter composed of JK flip-flops:
If the signal is output from the Q terminal, it is an adder counter;
if the signal is output from the terminal, it is a subtractor counter.
Design idea: The key is to use the add/subtract control signal to add the output signal of the Q terminal or terminal to the T input terminal of the adjacent high-bit T flip-flop.
Figure 7.3.11 shows the logic diagram of a three-bit synchronous binary add/subtract counter.

M is the plus/minus control signal, and its value can be 1 or 0.

From the figure, we can get the driving equations of the three T flip-flops respectively:

Figure 7.3.12 in the textbook shows the logic diagram of the 8421BCD synchronous decimal adder counter composed of JK flip-flops, triggered by falling edges.
Analyze its working principle. (Consolidate the analysis method of synchronous sequential circuits, which can be learned by students themselves)
Logical function: the same as the asynchronous decimal counter.

3. Integrated Synchronous Counter

1. Logic function diagram of the integrated decimal synchronous adder counter CT74LS160
. It is basically the same as CT74LS161, but the model is different.
Function table. It is exactly the same as CT74LS161.
Main function. It is basically the same as CT74LS161, but it realizes decimal counting.
Carry output signal CO = CTT Q3Q0 = Q3Q0

[Example 7.3.4] Try to use CT74LS160 to form a seven-bit counter.
Solution: Use the synchronous reset control terminal to reset to zero.
(1) Write the binary code of SN-1
SN-1 = S7-1 = S6 = 0110
(2) Write the feedback reset (set) function. Assume that the counter starts counting from 0. To do this, D3D2D1D0 = 0000, so (7.3.11)

(3) Draw a connection diagram. Draw a connection diagram according to formula (7.3.11) and the requirements of setting numbers, as shown in Figure 7.3.14.

After-class thinking question: Use the asynchronous reset control terminal of CT74LS160 to form a seven-base counter.

2. Integrated decimal synchronous up/down counter CT74LS190

⑶ Main logical functions. (Analyze according to the function table, no need to write on the blackboard)

7.3.3B Using counter cascade to obtain a large-capacity synchronous N-base counter
I. Cascade method

Counter cascade is to connect multiple integrated counters (such as M1-base, M2-base) in series to obtain an N-base counter with a larger counting capacity (=M1×M2).

Generally, integrated counters are equipped with cascade input and output terminals.
The implementation method of synchronous counters:
low-bit carry signal → high-bit hold function control terminal (equivalent to the T terminal of the trigger)
has high-bit counting function when there is carry; high-bit hold function when there is no carry.

Two CT74LS160s are cascaded into a 100-base synchronous adder counter.
As can be seen from the figure: before the low-order chip CT74LS160 (1) counts to 9, its carry output CO = Q3Q0 = 0, and the high-order chip CT74LS160 (2) CTT = 0, maintaining the original state unchanged. When the low-order chip counts to 9, its output CO = 1, that is, the high-order chip CTT = 1, at this time, the high-order chip can receive the count pulse input from the CP terminal. Therefore, when the 10th count pulse is input, the low-order chip returns to the 0 state, and the high-order chip adds 1 at the same time.

2. Feedback Zeroing Method

Two 4-bit binary adding counters CT74LS161 are cascaded into a fiftie-decimal counter.

Modern teaching methods and means: Demonstrate the logical functions of 74LS161, 74LS160, 74LS190 using DLCCAI or EWB