What is dsp technology

Digital Signal Processing (DSP) is an emerging discipline that involves many disciplines and is widely used in many fields. Since the 1960s, with the rapid development of computer and information technology, digital signal processing technology has emerged and developed rapidly. In the past two decades, digital signal processing has been widely used in fields such as communications.

Digital signal processing is the use of computers or special processing equipment to collect, transform, filter, evaluate, enhance, compress, identify and process signals in digital form to obtain a signal form that meets people's needs.

Digital signal processing is developed around the theory, implementation and application of digital signal processing. The development of digital signal processing in theory has promoted the development of digital signal processing applications. In turn, the application of digital signal processing has promoted the improvement of digital signal processing theory. The implementation of digital signal processing is the bridge between theory and application.

Digital signal processing is based on many disciplines and covers a wide range of areas. For example, in the field of mathematics, calculus, probability statistics, random processes, numerical analysis, etc. are all basic tools for digital signal processing. It is also closely related to network theory, signals and systems, control theory, communication theory, fault diagnosis, etc. Some emerging disciplines, such as artificial intelligence, pattern recognition, neural networks, etc., are inseparable from digital signal processing. It can be said that digital signal processing takes many classical theoretical systems as its theoretical basis, and at the same time makes itself the theoretical basis of a series of emerging disciplines.

The world's first single-chip DSP chip should be the S2811 released by AMI in 1978. The commercial programmable device 2920 released by Intel in 1979 was a major milestone in DSP chips. Neither of these two chips had a single-cycle multiplier that is required of modern DSP chips. In 1980, the μPD7720 launched by NEC of Japan was the first commercial DSP chip with a multiplier.

After that, the most successful DSP chips are the series of products of Texas Instruments (TI). In 1982, TI successfully launched its first-generation DSP chip TMS32010 and its series products TMS32011, TMS320C10/C14/C15/C16/C17, etc., and then successively launched the second-generation DSP chips TMS32020, TMS320C25/C26/C28, the third-generation DSP chips TMS320C30/C31/C32, the fourth-generation DSP chips TMS320C40/C44, the fifth-generation DSP chips TMS320C5X/C54X, the improved version of the second-generation DSP chip TMS320C2XX, the high-performance DSP chip TMS320C8X integrating multiple DSP chips, and the sixth-generation DSP chips TMS320C62X/C67X, which are currently the fastest. TI classifies commonly used DSP chips into three series, namely: TMS320C2000 series (including TMS320C2X/C2XX), TMS320C5000 series (including TMS320C5X/C54X/C55X), TMS320C6000 series (TMS320C62X/C67X). Today, TI's series of DSP products have become the most influential DSP chips in the world. TI has also become the world's largest DSP chip supplier, with its DSP market share accounting for nearly 50% of the world's share.

Comparison between DSP processor and general processor

Consider an example of digital signal processing, such as a finite impulse response filter (FIR). In mathematical terms, a FIR filter is a series of dot products. It takes an input quantity and an ordinal vector, multiplies the coefficients and the sliding window of input samples, and then adds all the products together to form an output sample.

Similar operations are repeated in large quantities during digital signal processing, so devices designed for this purpose must provide dedicated support, which has led to the separation of DSP devices and general-purpose processors (GPPs):

1. Support for dense multiplication operations

GPPs are not designed to do dense multiplication tasks, and even some modern GPPs require multiple instruction cycles to do a multiplication. DSP processors use specialized hardware to implement single-cycle multiplication. DSP processors also add accumulator registers to handle the sum of multiple products. Accumulator registers are usually wider than other registers, adding extra bits called result bits to avoid overflow.

At the same time, in order to fully realize the benefits of specialized multiplication-accumulation hardware, almost all DSP instruction sets contain explicit MAC instructions.

2. Memory structure

Traditionally, GPP uses the von Neumann memory structure. In this structure, there is only one memory space connected to the processor core through a set of buses (an address bus and a data bus). Typically, four memory accesses will occur to perform a multiplication, which takes at least four instruction cycles.

Most DSPs use the Harvard structure, which divides the memory space into two, storing programs and data respectively. They have two sets of buses connected to the processor core, allowing them to be accessed simultaneously. This arrangement doubles the bandwidth of the processor memory, and more importantly, provides data and instructions to the processor core at the same time. Under this layout, the DSP can implement single-cycle MAC instructions.

There is also the problem that today's typical high-performance GPP actually contains two on-chip caches, one for data and one for instructions, which are directly connected to the processor core to speed up access at runtime. Physically, this dual memory and bus structure on chip is almost the same as the Harvard structure. However, logically, there are important differences between the two.

GPP uses control logic to determine which data and instruction words are stored in the on-chip cache, without the programmer's knowledge (and perhaps without the programmer's knowledge). In contrast, DSP uses multiple on-chip memories and multiple sets of buses to ensure multiple memory accesses per instruction cycle. When using DSP, the programmer explicitly controls which data and instructions are stored in on-chip memory. When writing programs, the programmer must ensure that the processor can effectively use its dual buses.

In addition, DSP processors almost never have data caches. This is because typical data for DSP is a data stream. That is, after the DSP processor performs calculations on each data sample, it is discarded and rarely reused.

3. Zero Overhead Loop

If you understand a common characteristic of DSP algorithms, that is, most of the processing time is spent executing small loops, it is easy to understand why most DSPs have dedicated hardware for zero-overhead loops. The so-called zero-overhead loop means that the processor does not spend time checking the value of the loop counter, conditionally transferring to the top of the loop, and decrementing the loop counter by 1 when executing the loop.

In contrast, GPP loops are implemented in software. Some high-performance GPPs use branch prediction hardware to achieve nearly the same effect as hardware-supported zero-overhead loops.

4. Fixed-point calculation

Most DSPs use fixed-point calculations instead of floating-point. Although DSP applications must pay great attention to digital accuracy, it should be much easier to do it with floating-point, but for DSP, cheapness is also very important. Fixed-point machines are cheaper (and faster) than corresponding floating-point machines. In order to avoid using floating-point machines while ensuring digital accuracy, DSP processors support saturation calculations, rounding, and shifting in both instruction sets and hardware.

5. Specialized addressing method

DSP processors often support specialized addressing modes that are useful for common signal processing operations and algorithms. For example, block (loop) addressing (useful for implementing digital filter delay lines) and bit-reversal addressing (useful for FFTs). These very specialized addressing modes are not often used in GPPs and can only be implemented in software.

6. Prediction of execution time

Most DSP applications (such as cell phones and modems) are strictly real-time applications, where all processing must be completed within a specified time. This requires the programmer to determine exactly how much processing time is required for each sample, or at least to know how much time is required in the worst case.

If you plan to use a low-cost GPP to complete real-time signal processing tasks, execution time prediction will probably not be a problem, because low-cost GPPs have a relatively straightforward structure and are more easily predictable in execution time. However, most real-time DSP applications require processing power that low-cost GPPs cannot provide.

At this point, the advantage of DSPs over high-performance GPPs is that even with cached DSPs, it is the programmer (not the processor) who decides which instructions go in, so it is easy to tell whether instructions are read from cache or memory. DSPs generally do not use dynamic features such as branch prediction and speculative execution. Therefore, it is completely straightforward to predict the required execution time for a given piece of code. This allows the programmer to determine the performance limits of the chip.

7. Fixed-point DSP instruction set

The fixed-point DSP instruction set is designed with two goals in mind:

Enables the processor to complete multiple operations in each instruction cycle, thereby improving the computational efficiency of each instruction cycle.

Minimize the memory space used to store the DSP program (this issue is particularly important in cost-sensitive DSP applications because memory has a significant impact on the cost of the entire system).

To achieve these goals, the instruction set of DSP processors usually allows programmers to specify several parallel operations in one instruction. For example, a single instruction contains MAC operations, that is, one or two data moves at the same time. In a typical example, a single instruction contains all the operations required to calculate one section of an FIR filter. The price paid for this high efficiency is that its instruction set is neither intuitive nor easy to use (compared to the GPP instruction set).

GPP programmers usually don't care whether the processor's instruction set is easy to use, because they generally use high-level languages ​​such as C or C++. Unfortunately for DSP programmers, most DSP applications are written in assembly language (at least partially assembly language optimized). There are two reasons for this: First, most widely used high-level languages, such as C, are not suitable for describing typical DSP algorithms. Second, the complexity of the DSP structure, such as multiple memory spaces, multiple buses, irregular instruction sets, highly specialized hardware, etc., makes it difficult to write an efficient compiler for it.

Even if you use a compiler to compile C source code into DSP assembly code, the optimization task is still heavy. Typical DSP applications have a lot of computing requirements and strict overhead constraints, making program optimization essential (at least for the most critical parts of the program). Therefore, a key factor in considering the selection of DSP is whether there are enough programmers who can better adapt to the DSP processor instruction set.

8. Requirements for development tools

Because DSP applications require highly optimized code, most DSP vendors provide some development tools to help programmers complete their optimization work. For example, most vendors provide processor simulation tools to accurately simulate the processor's activities in each instruction cycle. These are very useful tools for ensuring real-time operation or code optimization.

GPP vendors usually do not provide such tools, mainly because GPP programmers usually do not need this level of detailed information. The lack of GPP simulation tools accurate to the instruction cycle is a big problem faced by DSP application developers: since it is almost impossible to predict the number of cycles required by a high-performance GPP for a given task, it is impossible to explain how to improve the performance of the code.