Working Principle of Satellite Digital TV Receiver

The satellite digital TV receiving system generally consists of three parts: a receiving antenna (including feed source), a low-noise downconverter (high-frequency head LNB) and a satellite digital TV receiver. The antenna and high-frequency head are called outdoor units, and the satellite digital TV receiver is called an indoor unit, or an integrated decoding receiver (
IRD), which is the result of the integration of contemporary computer technology, digital communication technology and microelectronics technology.

1 Functional block diagram of IRD

The general functional block diagram of IRD is shown in Figure 1. As can be seen from the figure, a typical IRD includes: tuner, second IF signal demodulation, channel decoding, MPEG-2 transport stream demultiplexing, MPEG-2 audio/video decoding and analog audio/video signal processing.

2. Channel receiving module

The satellite downlink signal of C band or Ku band is received by the dog line, amplified and down-converted by LNB to form the first intermediate frequency signal of 950~2050 MHz, which is sent to the tuner of IRD via cable. The high-frequency tuner controls the local oscillator frequency through the PLL (phase-locked loop) loop according to the required received frequency, and converts the input signal into the second intermediate frequency (479.5 MHz) signal, which is sent to the orthogonal phase detector to decompose I and Q analog signals. The two analog signals are converted into 6-bit parallel digital signals respectively through the A/D converter and enter the QPSK demodulation circuit and channel error correction circuit.

The core part of the QPSK demodulator plays the role of carrier recovery, addressing, bit synchronization, anti-aliasing, matched filtering and automatic gain control (AGC).

The Butterworth matched filter is used to complete the pulse forming filter transformation of the raised cosine roll-off shape (α=0.35DVB or α=0.20DSS, DVB digital video broadcasting, DSS digital satellite service).

The channel error correction part includes: Viterbi convolution (1/2, 2/3, 3/4, 5/6, 6/7 and 7/8, K=7) and RS decoding (204, 188DVB). Viterbi decoding can correct data streams with a bit error rate (BER) of 10^-4 to 10^-2 to achieve an RFR of 10-4. RS decoding mainly corrects sudden sheet errors to achieve a BER better than 10^-10, and finally outputs a transport stream (TS) that complies with the MPEG-2 standard, with each data packet being 188 bytes. The early channel receiving module was completed by two integrated circuits, such as the domestic xowJ-1 type IRD, which uses the integrated circuit STV0190 to complete the dual-channel A/D conversion, and the integrated circuit STV0196 to complete the QPSK demodulation and forward error correction FEC. At present, the functions of the above two integrated circuits have been combined into one chip, such as: STVD0199, ODM8511, etc.

3. Demultiplexing module

TS code stream is a data stream formed by multiple program data packets (including video, audio and data information) multiplexed according to the MPEG protocol. Therefore, before decoding, the TS stream must be demultiplexed, and the corresponding video, audio and data packets must be extracted according to the packet identification number (PID) of the program to be viewed, and the packaged program elementary stream (PES) that complies with the MPEG standard must be restored.

The demultiplexer chip integrates 32 user-programmable PID filters. One is for video PID, one is for audio PID, and the remaining 30 can be used for filtering program special information (PSI), service information (SI) and dedicated data. PID processing is divided into two steps:

(1) PID preprocessing: Only PID matching selection is performed, and packets with mismatched PID values ​​are filtered out, picking out the data packets of the desired viewing program.

(2) PID post-processing: Perform transport stream (TS) layer error checking (including packet loss, PID discontinuity, etc.), filter out the packet header and adjustment segment of the transport packet, find the payload, connect it in a certain order, and combine it into an F'ES stream.

The system clock is 27 MHz and is generated by a voltage-controlled oscillator (VCXO). The PLL loop is controlled by extracting the program clock reference (PCR) in the bit stream to synchronize the system clock of the IRD with the clock of the input program.

The chip also has an embedded RIsc cPU, which has strong processing capabilities and can handle complex system tasks of IRD together with the system software, such as: transmitting subtitles, on-screen display (OSD), teletext, electronic program guide (EPC), etc.

The DRAM controller supports 16 MB DRAM (dynamic random access memory), which is shared by the CPU, transmission and other functions. Demultiplexing chips include CL9110, ST20-TP2, etc.

4 MPFG-2 decoding module

The video data stream and PCM audio data stream in CCIR601 format are sent to the video encoder and audio DAC (digital-to-analog converter) to generate analog TV signals according to a certain TV standard (PAL or NTSC) for TV reception. The structure of a general PEG-2 decoder is shown in Figure 2.

The MPEG-2 decoding modules currently under development integrate the system demultiplexing modules together, sometimes called single-chip microcomputers, such as: ST's (Thomson of France) sTi5500, 5505, 5512, 5518, Hyundai's ODM8211, Fujitsu's MB87L2250 and LSI's SC2000. Beijing Haier has also developed a commercially available MPEG-1 decoding chip named "Patriot One".

The additional functional modules of IRD include conditional access module IC card interface, video/audio output interface, data stream interface, remote control and power supply.