NE567 Tone Decoder Principle and Application

NE567 tone decoder contains a phase-locked loop and can be widely used in various circuits such as BB machines and frequency monitors.
Tone Decoder This article discusses the phase-locked loop circuit and introduces the NE567 single-chip tone decoder integrated circuit. This tone decoder block contains a stable phase-locked loop and a transistor switch. When the predetermined audio is added to the input of this integrated block, a ground wave can be generated. This tone decoder can decode tones of various frequencies. For example, detecting the key tone of a telephone. This tone decoder can also be used in BB machines, frequency monitors and controllers, precision oscillators, and telemetry decoders. This article mainly discusses Philip's NE567 tone decoder/phase-locked loop. This device is a low-cost 567-type product in an 8-pin DIP package. Figure 1 shows the pin diagram of this package. Figure 2 shows the internal block diagram of this device. It can be seen that the basic components of NE567 are a phase-locked loop, a right-angle phase detector (orthogonal phase detector), an amplifier, and an output transistor. The phase-locked loop contains a current-controlled oscillator (CC0), a phase detector, and a feedback filter. Philip's NE567 has a certain temperature operating range, that is, 0 to +70°F. Its electrical characteristics are roughly the same as Philip's SE567, except that the operating temperature of SE567 is -55 to 125°F. However, 567 has been established as an industry standard tone decoder, and several other multinational semiconductor integrated circuit manufacturers also produce this integrated circuit. For example, Analg Device offers three AD567s, EXar offers five XR567s, and National Sevniconductor offers three LM567s. These different brands of 567 devices can all work properly in the circuit discussed in this article. Therefore, this article will refer to these devices as 567 tone decoders below. 567 Basics The basic working condition of 567 is like a low-voltage power switch. When it receives an input tone within a selected narrow frequency band, the switch is turned on. In other words, 567 can be used as a precision tone control switch. The general 567 can also be used as a variable waveform generator or a general phase-locked loop circuit. When used as a tone control switch, the detected center frequency can be set to any value within 0.1 to 500KHz, and the detection bandwidth can be set to any value within 14% of the center frequency. In addition, the output switch delay can be changed over a wide time range by selecting external resistors and capacitors. The current-controlled 567 oscillator can change its oscillation frequency over a wide frequency band through external resistor R1 and capacitor C1, but can only change its oscillation frequency over a very narrow frequency band (the maximum range is about 14% of the free oscillation frequency) through the signal on pin 2. Therefore, the 567 phase-locked circuit can only "lock" within a very narrow frequency band of the preset input frequency value. The 567's integral phase detector compares the relative frequency and phase of the input signal and the oscillator output. Only when these two signals are the same (i.e., the phase-locked loop is locked) will a stable output be produced. The center frequency of the 567 tone switch is equal to its free oscillation frequency, and its bandwidth is equal to the locking range of the phase-locked loop. Figure 3 shows the basic wiring diagram of the 567 when used as a tone switch. The input tone signal is AC coupled to pin 3 through capacitor C4, where the input impedance is about 20KΩ. The external output load resistor RL inserted between the positive power supply terminal and pin 8 is related to the power supply voltage. The maximum value of the power supply voltage is 15V, and pin 8 can absorb a load current of up to 100mA. Pin 7 is usually grounded, and pin 4 is connected to the positive power supply, but its voltage value must be a minimum of 4.75V and a maximum of 9V. If you pay attention to throttling, pin 8 can also be connected to the positive power supply of pin 4. The center frequency (f0) of the oscillator is also determined by the following formula: f0 = 1.1 × (R1 × C1)·················· (1) Here the unit of resistance is KΩ, the unit of capacitance is uF, and the unit of f0 is KHz. By shifting the terms in equation (1), we can get the value of capacitor C1: C1 = 1.1/(f0×R1)·················(2) Using these two formulas, the values ​​of capacitor and resistor can be determined. The value of resistor R1 should be in the range of 2 to 20KΩ. Then, the capacitor value is determined by equation (2). This oscillator generates an exponential sawtooth wave on pin 6 and a square wave on pin 5. The bandwidth of this tone switch (and the locking range of the PLL) is determined by C2 and a 3.9KΩ resistor inside the 567. The output switch delay of this circuit is determined by C3 and a resistor inside the integrated circuit. Table 1 lists the electrical characteristics of Philip's NE567. The characteristics of all other manufacturers' 567 chips of different brands are roughly the same as those in Table 1.

Table 1

Oscillator Design Figures 4 and 5 show how to make the 567 produce a precise square wave output. A nonlinear sawtooth wave can be obtained from pin 6, but its use is limited. However, a square wave with excellent performance can be obtained at pin 5. As shown in Figure 4, the rise and fall time of the output square wave is 20nS. The peak-to-peak amplitude of this square wave is equal to the power supply voltage minus 1.4V. This square wave generator and load characteristics are excellent. Any resistive load greater than 1KΩ will not affect the function of the circuit. In addition, the output of this square wave generator can also be added to a low impedance load. As shown in Figure 5, the peak current at the output of pin 8 is as high as 100mA, but the waveform is slightly worse. Using the above oscillation frequency and capacitance calculation formulas (1) and (2), the various parameters of this type of oscillator can be determined. Similarly, R1 must be limited to the range of 2 to 20KΩ. To simplify the calculation and save time, the values ​​of the components that determine the oscillation frequency can also be read directly from the nomogram shown in Figure 6. For example, if the 567 oscillator is required to operate at 10KHz, the values ​​of C1 and R1 can be 0.055uF and 2KΩ, or 0.0055uF and 20KΩ. By applying a control voltage to pin 2 of the 567, the operating frequency of the oscillator can be fine-tuned within a narrow range by a few percent. If a control voltage is applied, pin 2 should be connected to a decoupling capacitor C2, whose value should be approximately twice that of C1. The circuits of Figures 4 and 5 can be modified in different ways, as shown in Figures 7 to 10. In Figure 7, the duty cycle or mark/space ratio of the waveform generated is fully variable, and its range of variation is 27:1 to 1:27 with the help of trimmer potentiometer R2. In addition, during each operating cycle, C1 is alternately charged and discharged, charging through the left side of resistor R1, diode D1 and R2, and discharging through the right side of resistor R1, diode D2 and R2. Only the operating frequency changes slightly with the change of the mark/space ratio. The circuit shown in Figure 8 can generate orthogonal square waves. The two square wave outputs of this oscillator on pins 5 and 8 have a phase difference of 90°. In this circuit, input pin 3 is grounded. If a bias voltage of more than 2.8V is applied to pin 3, the square wave on pin 8 has a phase shift of 180°. Figures 9 and 10 show circuits of oscillators with a maximum timing resistor value of about 500KΩ. In this way, the value of timing capacitor C1 can be reduced proportionally. In these two circuits, there is a buffer stage between pin 6 of 567 and the node of R1 and C1. In Figure 9, this buffer stage is a first-stage transistor emitter follower. Unfortunately, the introduction of this stage makes the symmetry of the waveform slightly worse. Correspondingly, the circuit shown in Figure 10 uses a first-stage operational amplifier follower as a buffer stage. This does not affect the symmetry of the waveform. Five outputs of 567 Five output terminals of 567. Two of them (pins 5 and 6) provide the output waveform of the oscillator, while the third output terminal, pin 8, is the main output port of 567 as mentioned above. The remaining two outputs are pins 1 and 2 of the decoder. Pin 2 is connected to the phase detector output of the phase-locked loop and is internally statically biased to 3.8V. When the 567 receives an in-band input signal, this bias voltage changes accordingly, and the change in bias voltage is linear with the input signal frequency in the typical range of 0.95 to 1.05 times the oscillator free-running frequency. Its slope is 20mV per 1% of frequency deviation (i.e. 20mV/f0). Figure 11 shows the time relationship between the output of pin 2 and the output of pin 8 when the 567 is used as a tone switch. The time relationship is shown in the figure under two bandwidths (14% and 7%). Pin 1 gives the output of the 567 orthogonal phase detection. When the tone is locked, the average voltage on pin 1 is a function of the amplitude of the in-band input signal of this circuit, as shown in the transfer function of Figure 12. When the average voltage on pin 1 is pulled down below the 3.8V threshold, the internal output transistor with the collector on pin 8 is turned on. Determination of bandwidth When 567 is used as a tone switch, the maximum value of its bandwidth (percentage of center frequency) is about 14%. This value is proportional to the in-band signal voltage of 25 to 250mV RMS. However, when the signal voltage changes from 200 to 300mV, the bandwidth is not affected. At the same time, the bandwidth is inversely proportional to the product of the center frequency f0 and capacitor C2. The actual bandwidth is: BW = 1070 BW is in the unit of percentage (%) of the center frequency, and Vi≤200mVRMS. The unit of Vi is V-RMS and the unit of C2 is uF. C2 is selected by trial and error processing. At the beginning, the value of C2 can be selected to be twice that of C1. Then the value of C2 can be increased to reduce the bandwidth, or the value of C2 can be reduced to increase the bandwidth. Detection of bandwidth symmetry The so-called detection of the symmetry of the plastic surgery is to measure the degree of symmetry of this bandwidth and the center frequency. Symmetry is defined as follows: (fmax + fmin - 2f0) / 2f where fmax and fmin are the frequencies corresponding to the two edges of the detected frequency band. If a tone switch has a center frequency of 100 kHz and a bandwidth of 10 kHz, the edge frequencies of the band are symmetrical at 95 kHz and 105 kHz, so that its symmetry is 0%. However, if the band is quite asymmetrical, with edge frequencies at 100 kHz and 110 kHz, the symmetry value increases to 5%. If necessary, an external bias trimming voltage can be applied to pin 2 of the 567 using trimmer potentiometer R2 and 47KΩ resistor R4 to reduce the symmetry value to 0, as shown in Figure 13. Moving the center sliding contact of the potentiometer upward reduces the center frequency, and moving it downward increases the center frequency. Silicon diodes D1 and D2 are used for temperature compensation. Tone Switch Design It is easy to design a practical tone switch based on the typical circuit shown in Figure 3. The values ​​of the frequency control elements resistor R1 and capacitor C1 can be selected using the nomogram of Figure 6. The value of capacitor C2 can be determined experimentally based on the above discussion. A capacitor twice the value of C1 can be used initially, and then its value can be adjusted if necessary to give the required signal bandwidth. If the symmetry of the frequency band is strict, a symmetry adjustment stage can be added as shown in Figure 13. Finally, make the value of C3 twice that of C2. And check the response of this circuit. If C3 is too small, the output at pin 8 may pulse during the switching period due to the transition process. If C3 is selected appropriately, the entire circuit design is complete. Multiplexer Switch Any number of 567 tone switches can be fed from an audio input to form a multi-tone switch network of any desired size. Figures 14 and 15 are two practical two-stage switch networks. The circuit in Figure 14 acts as a dual-tone decoder. When either of the two input signals is present, a signal output can be stimulated. In the figure, the two tone switches are excited by a signal source, and their outputs are processed by a CD4001B CMOS gate integrated circuit. Figure 15 shows two 567 tone switches connected in parallel, which act as a single tone switch with a relative bandwidth of 24%. In this circuit, the operating frequency of IC1 tone switch is designed to be 1.12 times higher than that of IC2 tone switch. Therefore, their switching bands are overlapping.