Next-generation packaging technology for cardiac rhythm management (CRM) applications

The medical profession is a conservative and slow-to-change industry, and rightfully so. Because the lives of patients are at stake, conservative tendencies often go hand in hand with recognized safety and effectiveness. However, given the current healthcare environment, with trends such as managed care, large procurement, and government contracts, designers of implantable medical devices and other consumer medical products are under pressure to reduce costs. In addition, designers must reduce the product's form factor, improve performance, and maintain high reliability levels.

Life-threatening cardiac rhythm management (CRM) products, such as implantable pacemakers and implantable cardioverter-defibrillators (ICDs), are inevitably subject to these pressures. Because these devices are implanted in the human body, reliability is extremely important. A single mandatory product recall can have serious consequences, not only affecting the financial bottom line of the companies involved, but also affecting the lives of patients. All implantable medical devices are under pressure to reduce size, increase functionality, and extend battery life.

All of these pressures require improvements to current packaging technologies. Smaller devices are less intrusive and less noticeable to patients than larger devices, require smaller incisions, cause less discomfort during treatment, and allow for faster recovery.

With smaller electronic processes, more options can fit into the package, such as RF transceivers for wireless communications, advanced sensors to optimize timed pacing and defibrillation shocks, and backup systems for use in the event of a primary system failure. Integrated circuits take advantage of advances in dense packaging such as wafer stacking. In most cases, discrete components will not change significantly. However, market pressures are beginning to require further improvements in existing discrete components.

CRM Applications

A pacemaker is designed to replace the electrical impulses produced by a healthy heart's sinus node. An irregular heartbeat occurs when the heart beats too fast, too slow, or irregularly. By placing the pacemaker in the right place and delivering electrical impulses at the right strength, the irregular heartbeat can be corrected. While the sinus node is generating its own electrical signals, the pacemaker does nothing but monitor. Some pacemakers also have a beat-rate adaptation feature, which means they monitor the heart's activity level and change the beat rate accordingly. Pacemakers can have one or two leads. A pacemaker with one lead is called a single-chamber pacemaker. Where the lead is placed depends on where the heart signal problem occurs. A pacemaker with two leads is called a bi-chamber pacemaker: one lead is placed in the right atrium and the other in the right ventricle. The type of pacemaker you need depends on the type of arrhythmia you have and the overall function of your heart.

An ICD has all the functions of a pacemaker, but can also deliver a high-voltage shock to the heart when the heart muscle loses its normal rhythm and begins to fibrosis. The advanced electronics send a large DC current to the heart, stopping all irregular heart activity and giving the sinus node a chance to control the heart rhythm.

In a typical ICD (see Figure 1), the housing contains a battery, a pulse generator, and a connector module. The pulse generator contains all the electrical circuitry for the CRM device.

Figure 1 Structure of an implantable cardioverter-defibrillator (ICD)

Power Management

Power management for CRM devices is critical. Battery replacement is difficult and expensive, and as patients live longer, battery life is important. The current goal for CRM devices is to ensure that the battery lasts seven to ten years before needing replacement.

Sensing and control components

The sensing and control portion of the CRM device contains a microprocessor for calculations, memory for code/parameter storage, a pulse generator to deliver an electric shock when needed, and a sensor amplifier for monitoring. To reduce size and save cost, these functions are integrated into one or more integrated circuits. Most ICs operate at low voltages to save power, typically less than 3.3V. These low-voltage circuits are sensitive to electrostatic discharge (ESD) and must be protected by electrical isolation. The sensing technology is already integrated into the electrodes or implanted sensors. The electrical pulses are delivered to the heart through leads, which are connected to the pulse generator through a connector module.

High voltage charging

During the charging phase, the CRM device draws energy from the lithium-ion battery and boosts it from approximately 4V to over 700V. The high voltage is used to defibrillate the heart. When a period of ventricular fibrillation is detected, energy is drawn from the battery to charge one or more energy storage capacitors. A high-voltage rectifier is used to control the voltage at this stage.

Switching Devices

The switch is used to direct the high voltage pulses from the charging stage to the heart leads. Various high voltage devices are used in the switching stage, including: insulated gate bipolar transistors (IGBTs), silicon controlled rectifiers (SCRs), metal oxide semiconductor field effect transistors (MOSFETs), rectifier diodes, and remote gated thyristors (RGTs). When selecting these devices, designers need to choose between the complexity of the drive circuit, the performance of the device, and the overall circuit board footprint of the device.

Power switches share common characteristics. First, they are large, with ratings up to 1600 V and 50 A. ICDs deliver large, high-energy pulses for very short periods of time, typically just a few milliseconds. There is very little time to dissipate the heat, so the silicon must absorb the energy. Second, both sides of the chip are live and require connections, which makes assembly difficult (in contrast to integrated circuits, which are live on only one side and require electrical connections only on the top). Third, high-voltage pulses have their own characteristics and can cause arcing in unwanted locations. Component spacing, wire bonds, and protective coatings become important considerations.

ESD and transient voltage protection

Transient voltage suppression (TVS) diodes are used to protect sensitive electronics. The diodes shunt any stray electrical pulses induced by the cardiac leads or casing to ground. These pulses can come from strong magnetic field sources such as medical equipment, arc welding equipment, car engines, or external defibrillators. Energy pulses generated inside the casing are also a concern. When the ICD delivers its high voltage pulses, the sensitive integrated circuit electronics must be isolated. The control stage is protected by power switches to block any stray energy, and these blocking switches are generally controlled by MOSFETs.

Evolving Electronic Device Packaging

Advances in substrate assembly have allowed medical device manufacturers to continue to reduce the size of CRM devices. Chip-on-board assembly, chip-on-chip, and today’s advanced 2D and 3D packaging are widely prevalent in the industry. These technologies reduce the overall circuit area by 60-80%. Chip stacking reduces internal interconnects, improves test results, and enables the use of mixed wafer process technologies in a small area. However, the reduction in circuit footprint comes at the expense of more expensive materials and cumulative yield issues. While advances have been made in reducing the size of discrete components, transformers, capacitors, and battery packaging, power discrete packaging technology has lagged behind.

The high-power components used in implantable medical devices, such as IGBTs, SCRs, MOSFETs, and rectifiers, present unique layout challenges to circuit designers. First, handling the larger power requires the use of large chips. Second, electrical contacts are required on both the top and bottom of the device. Third, high-voltage arcing must be controlled. Designers are looking for packaging solutions that can eliminate arcing, coatings, and wire bonds while minimizing the board size. A chip-scale, flip-chip power package is needed that can bring the bottom contacts to the same plane as the top contacts.

Ceramic carrier

One way to create a planar flip-chip power package is to connect the chip to a ceramic carrier (see Figure 2). The ceramic carrier is shaped like an inverted L with metal traces embedded in the ceramic to guide the contacts on the bottom to the top. The chip is fixed to the ceramic carrier by brazing or epoxy to form a planar device. Both the chip and the ceramic carrier have solder bumps to complete the planar flip-chip connection, which can save overall space compared to traditional chip-and-lead packaging. In addition, the ceramic carrier has the advantage of good insulation properties to prevent high-voltage arcing.

Figure 2 Ceramic carrier

Despite these advantages, there are still manufacturing issues that need to be overcome. For example, the X, Y, and Z planes are a problem because the chip can move or tilt when attached to the carrier.

With the help of metal-filled silicon via (TSV) technology, the chip size can be expanded to make the non-charged silicon area adjacent to the charged silicon area. First, the hole is made through the silicon wafer, and then the hole is filled with metal to create a channel through the non-charged silicon area (see Figure 3), so that the contact at the bottom is transferred to the top. Now the current can pass from the charged area through the metal and TSV behind. Although this technology increases the chip size, the increase in chip size is less than that using a ceramic carrier.

The configuration shown in Figure 3 is just one potential variation. Other variations can be generated from this basic structure, for example by creating bottom contacts that allow for interposer connections or chip stacking.

Figure 3 Metal-filled silicon wafer through-holes

TSV is an emerging manufacturing process that is a promising solution for handling the high currents involved in power devices. However, at the recent International Interconnect Technology Symposium, VLSI Research observed that "mass production of TSV technology is still several years away." Before mass production, the processing cost per wafer remains high. Power device manufacturers have been researching lower-cost TSV solutions.

Silicon on insulator power chip

Power-silicon on insulator (PSOI?) is a hermetic chip-scale package that uses a different approach to bring electrical connections to the same side (see Figure 4). PSOI uses planar processing steps to develop charged areas on the same side and uses metallization to connect the areas. The top is sealed and protected by connecting an insulator on the top. External metallized contacts are developed on the bottom of the device, much like a flip-chip package. However, the bottom and sides of PSOI are insulated, forming a unique wafer-level package. The chips can be cut in any way: single, double, quartered, etc. This concept eliminates any back-end manufacturing steps. After being cut in wafer form, the product is tested and shipped in a suitable container, such as a stack or gel package that can be picked and placed automatically.

Figure 4 Silicon on insulator power wafer

Top, bottom and side insulators isolate the junction from environmental contamination and moisture. The process eliminates wire bonds and protective coatings, reducing overall chip size. PSOI can also be manufactured with a top contact that facilitates stacking, with excellent heat dissipation characteristics and small size while maintaining excellent performance. In addition, the process provides chip-to-chip electrical isolation and reduces parasitic effects. Depending on the current packaging technology used, the overall circuit footprint can be reduced by 20% to 55%.

Power chip stacking

Wire Bonding

The power chip stack currently used involves stacking two or more known-good dies and welding them together vertically. These designs use mature technologies, including interposers, welding, and wire bonding, to integrate various chip functions in a vertical manner. The main advantage of this approach is that it only requires half (or less) of the circuit board space and allows mixed wafer process technology. The main disadvantage is that wire bonding is still required (so there is still an arc problem), and the cumulative yield loss will push up production costs.

Folded Leads

Folded wire routing is another die stacking method that can be used. Using an origami-like folding method, the power die can be folded on top of each other. The trick is how to make contacts on the top and bottom of the power die while keeping the low side high without wire bonding. The cumulative yield loss is better than solder stacking the die.

Stacked Chips in BGA

While die stacking using wire bonding is an effective solution, the main drawbacks are the extra space required for the wires and reliability issues with bonding. Microsemi is developing an alternative solution that uses an innovative stacked die interconnect in BGA without the need for wire bonding. By using innovative die layout and interconnects, the solution has low parasitic inductance and safe high voltage transmission characteristics. The low-profile BGA (height of approximately 1mm) reduces the footprint by half and can use standard pick-and-place assembly techniques, thereby improving yield and reducing costs.

in conclusion

New CRM devices integrate new features and benefits, but it is becoming more difficult to maintain a competitive advantage in today's market. As the world's population ages and medical expenses grow in developing countries, CRMs remain an important market for implantable medical devices. Miniaturization, high performance and quality remain the main technical challenges for CRM design. Reducing the size of power devices cannot use next-generation lithographic node technology, but requires the use of 3D circuit packaging. Stacking power devices is a mature but costly approach because of the cumulative loss of electrical and mechanical yield. A new chip-scale packaging technology is needed that can handle high voltages and bring all contacts to the same side. New ceramic chip carriers, PSOI and leadless BGA technologies currently under development by Microsemi have the characteristics of low cost, high reliability and small footprint to meet the needs of future CRM designs.