1. ARM chip type

1. ARM Classification

(1) ARM classification type (chip | core | instruction architecture)

ARM Category:

-- ARM chip type: 6410, 2440, 210;

-- ARM core type: arm11, arm9, CortexA9;

-- Instruction architecture: armv7, armv6;

(2) Relationship between ARM chips and ARM cores

Relationship between chip and core: Chip contains core;

-- 2440 chip: including arm9 core;

-- 6410 chip: contains arm11 core;

-- 210 chip: including CortexA8 core;

(3) Relationship between ARM core and instruction architecture

Relationship between ARM core and instruction architecture:

-- ARM9: armv4 instruction architecture;

-- ARM11: armv6 instruction architecture;

-- CortextA8 : armv7 instruction architecture;

2. ARM Evolution

(1) Classic Camp

Development history: ARM7 --> ARM9 --> ARM11, ARM11 has the highest performance, ARM7 has the lowest performance;

(2) Cortex Camp

Cortext Series:

-- Cortex-M series: no operating system, aimed at industrial control field, similar to single-chip microcomputer;

-- Cortex-R series: oriented to real-time applications, emphasizing real-time performance, and capable of running operating systems;

-- Cortex-A series: mainly for multimedia applications, most of the current smartphones belong to this series;

Performance recursion: Cortex-M0 --> Cortex-M1 --> Cortex-M3 --> Cortex-M4 --> Cortex-R4 --> Cortex-A5 --> Cortex-A8 --> Cortex-A9;

(3) Comparison between Cortex and ARM

ARM vs Cortext:

-- ARM7: ARM 7 is similar to Cortex-M3, neither has an operating system. The performance of Cortex-M3 is slightly higher, but the performance is limited;

-- ARM9 and ARM11: ARM9 and ARM11 have similar performance to Cortex-R4, ARM11 is not as good as Cortex-A5, and far inferior to Cortex-A8 and Cortex-A9;

3. Chip performance comparison (processing speed | cache | memory interface | OS)

(1) Processing speed comparison

Chip processing speed comparison: Go to the chip manual corresponding to the chip and find the Clock & Power Management section to view the clock related parameters;

-- 6410: 533MHz ~ 667MHz;

-- 2440: 12MHz crystal oscillator corresponds to 405 ~ 532 MHz processing speed;

-- 210: 800MHz ~ 1GHz;

(2) Cache comparison

Chip cache comparison: Go to the chip manual corresponding to the chip;

-- 6410: 16K instruction cache, 16K data cache;

-- 2440: 16K instruction cache, 16K data cache;

-- 210: 32KB instruction cache, 32KB data cache;

(3) Memory interface comparison

Chip memory interface comparison: SDRAM is already obsolete;

-- 2440: Provides SDRAM memory interface;

-- 6410: Provides SDRAM and DDR memory interface;

-- 210: Provides two memory interfaces: DDR1 and DDR2;

(4) Supported operating systems

Comparison of chip supported operating systems: Go to the chip manual corresponding to the chip to search;

-- 6410: WinCE | Linux | Android;

-- 2440 : WinCE | Linux;

-- 210: WinCE | Linux | Android;

(5) Other business information

Chip business comparison:

-- 6410 : Continue to use;

-- 2440: Samsung announced the discontinuation of production;

-- 210 : Continue to use;

2. ARM working mode

Corresponding manual: ARM Architecture Reference Manual.pdf manual, available for download in this blog;

-- Chapter Content: Programmers' Model, A2.2 Page 41;

-- Manual download address: http://download.csdn.net/detail/han1202012/8324641

1. Processor operating mode

(1) ARM operating mode example

Working mode diagram: The picture is taken from the ARM Architecture Reference Manual.pdf manual, Page 41, Chapter A2.2;

(2) Introduction to ARM working mode

Working mode introduction:

-- User mode (usr): the mode in which ordinary applications run;

-- FIQ mode (fiq): fast interrupt mode;

-- IRQ mode (irq): normal interrupt mode;

-- Supervisor mode (svc): a protection mode provided for the operating system;

-- Abort mode (abt): A mode in which access to virtual memory causes an exception;

-- Undefined mode (und): undefined instruction mode;

-- System mode (sys): This mode is only available in armv4 and above versions;

Linux system working mode: the system runs in usr mode, the kernel runs in svc mode;

3. ARM Registers

Corresponding manual: ARM Architecture Reference Manual.pdf manual, available for download in this blog;

-- Chapter Content: Programmers' Model, A2.3 Page 42;

-- Manual download address: http://download.csdn.net/detail/han1202012/8324641

1. Register Introduction

Register Introduction:

-- Number of registers: ARM has 37 registers;

-- General registers: 31 general registers, the program counter is also a general register;

-- Status register: 6 status registers;

-- Diagram:

-- Register diagram: Screenshot from Page 43;

2. General registers

(1) General register classification

General register classification:

-- Ungrouped registers: R0 ~ R7;

-- Grouped registers: R8 ~ R14, the registers used in different modes are different;

-- Program counter: PC pointer, is R15;

(2) Analysis of commonly used general registers

R13 register: usually used as SP stack pointer;

R14 register: usually used as a link register;

-- Function 1: Save the function return address;

-- Function 2: When an exception occurs, it is mainly used to record the function return address;

R15 register: PC pointer, program counter;

3. Status register

(1) Reasons for the status registers corresponding to each mode

Status Register:

-- Diagram:

-- Status registers corresponding to each mode: When an interrupt occurs, the interrupt program is executed, and the corresponding CPRS needs to be saved to the SPRS_xxx register of the corresponding mode. For example, if the interrupt is currently in scv mode, the status register is saved to the SPSR_svc register. After the interrupt is executed, the status is written back from SPSR_svc to the CPRS register;

(2) CPSR register bit introduction

CRSR register introduction:

-- Diagram:

-- N digits: compare two numbers a and b, that is, do subtraction (ab), if a < b, the subtraction result is a negative number, N = 1; if a >= b, the subtraction result is a positive number or 0, N = 0;

-- Z bit: When comparing two numbers, Z = 1 only when the two numbers are equal;

-- I bit: When I = 1, no interruption can be generated;

-- F bit: When F = 1, fast interrupt cannot be generated;

-- M bit: occupies 5 bits 0 ~ 4, mainly used to indicate the processor mode, which can read the mode and set the mode, as shown below:

4. ARM addressing mode

Corresponding manual: ARM Architecture Reference Manual.pdf manual, available for download in this blog;

-- Chapter Content: Programmers' Model, A2.3 Page 42;

-- Manual download address: http://download.csdn.net/detail/han1202012/8324641

Addressing mode: The processor finds the operand of the instruction based on the information given by the instruction;

1. Immediate addressing

Introduction to immediate addressing:

-- Addressing process: The operand itself is given in the instruction, and the operand can be obtained at the same time when the instruction is fetched;

-- Operand: The operand taken from the instruction is the immediate value;

-- Addressing mode: This method of taking immediate data from instructions is called immediate addressing;

Immediate addressing example:

-- Example: ADD R0, R0, #0x3F;

-- Analysis: Add R0 + #0x3F and put the result into R0;

Immediate addressing requirements: The second source operand is suffixed with "#";

2. Register addressing

Introduction to register addressing: Use the value in the register as an operand;

-- Example: ADD R0, R1, R2;

-- Example analysis: Add the numbers in registers R1 and R2, and store the result in R0;

3. Register indirect addressing

Introduction to register indirect addressing: The operands stored in the register are in the memory, and the register stores the address of the memory;

-- Example: LDR R0, [R2];

-- Example analysis: Register R2 stores the memory address of the operand, and the operand is taken from the memory and stored in R0;

4. Base address indexing

Introduction to base-indexed addressing:

-- Base address register: A base address is stored in the register;

--Offset: An offset is given in the instruction, and is placed in brackets with the base register;

-- Example: LDR R0, [R1. #4];

-- Example analysis: Take the address from R1, then add 4 to the address, and take the data from the added address;

5. Relative Addressing

Relative addressing introduction: The current value of the PC pointer is the base address, the address number in the instruction is the offset, and the sum of the two is the effective address;

-- Example: When BL NEXT is pressed, the program will jump to NEXT and return to the original program after execution.

BL NEXT; Jump to NEXT to execute

... ...

NEXT

... ...

MOV PC, LR ; return from subroutine