MC9S12XS128 PWM Output Configuration

1. PWM resource introduction

1.1 MC9S12 PWM Characteristics

• 8 independent PWM channels with programmable period and duty cycle

• 4 clock sources

• Dedicated counter for each PWM channel

• Each channel can select the effective level polarity

• Each PWM channel can be enabled/disabled

• Each channel can select the alignment of the output waveform

• Resolution: 8 bits (8 channels); 16 bits (4 channels)

1.2 PWM 8-channel 8-bit pin

The chip pin distribution is as follows:

2. Introduction to PWM Registers

Before introducing the registers, let’s take a look at the PWM module block diagram.

From the block diagram, we can see that the PWM configuration is mainly divided into: clock selection, enable, polarity, alignment, PWM channel and other aspects for control. The following introduces each register one by one.

2.1 Clock Selection Register

2.1.1 Clock Source

PWM has four clock sources, the clock sources are as follows:

• Clock A （Ch 0, Ch 1, Ch 4, Ch 5）

• Clock SA （Scaled A; Ch 0, Ch 1, Ch 4, Ch 5）

• Clock B （Ch 2, Ch 3, Ch 6, Ch 7）

• Clock SB （Scaled B; Ch 2, Ch 3, Ch 6, Ch 7）

The clock source selection is controlled by the PWMCLK register, the register bits are as follows:

Register bit function

2.1.2 Frequency Divider

The clock frequency cannot be directly used as the clock frequency of the PWM timer. Generally, it must be divided before it can be used. The divider from the bus clock to the timer clock is as follows:

The PWMPRCLK register is used to independently select the pre-scaling coefficients of clock sources A and B. The register structure is as follows:

The relationship between the frequency division value and the register bit is as follows:

PWMSCLA and PWMSCLB correspond to the A and B timer division

PWMSCLA Register

PWMSCLB Register

Timer frequency calculation formula:

When PWM is all 0, the frequency division value is 255; the frequency division value is the same as the other values.

2.2 Timer Channel Registers

There are three main registers that control the duty cycle of the PWM output waveform.

PWM Channel Counter Registers (PWMCNTx): Timing counter, increments according to the set clock frequency, resets when 0 is written

This register can be read and written at any time, but writing any value to the counter will cause the counter to reset to $00, and the counter direction is set to count up.

PWM Channel Period Registers (PWMPERx): Period register, set the PWM duty cycle, write 255 to reset

PWM Channel Duty Registers (PWMDTYx): Duty cycle register, set the PWM duty cycle, write 255 to reset

2.3 PWM Polarity Selection Register

PWM Polarity Register (PWMPOL)

PPOLx——Pulse Width Channel x Polarity

• 1 = PWM channel x output is high at the beginning of the cycle and becomes low when it reaches the value set in the duty cycle register.

• 0 = The output of PWM channel x is low at the beginning of the cycle and becomes high when it reaches the value set in the duty cycle register.

Supplement PWMDTYx, PWMPERx, PPOLx three registers under critical conditions, PWM output

2.4 PWM Enable/Disable Register

PWM Enable Register (PWME)

Channel x Enable

• 1 = PWM channel x is enabled.

• 0 = PWM channel x is disabled.

2.5 PWM Output Alignment Register

The PWM output of MC9S12 has two alignment modes, left alignment and center alignment.

Align Left

In left-aligned mode, the 8-bit counter is configured as an upward accumulating counter, which is compared with the duty cycle register and the period register. When the values ​​in the PWM counter and the duty cycle counter are equal, the output flips, and when the values ​​of the PWM counter and the period register match, the counter is reset and the period and duty cycle counter values ​​are loaded from the double buffer at the same time. The counter counts from 0 to the period register -1.

Center Alignment

In this mode, the 8-bit counter acts as an up & down counter. When the counter value is 0, it counts up. The counter is compared with the duty cycle register and the period register. When the PWM counter matches the duty cycle register value, the output flips. The PWM counter matches the period register and changes the counter direction from up counting to down counting. When the PWM counter decrements and matches the duty cycle counter again, the output changes again. When the PWM counter decrements to 0, the counting direction changes from down counting to up counting, and the period register and duty cycle register values ​​are loaded from the double buffer. The counter is added from 0 to the value in the period register and subtracted back to 0, so the effective period is PWMPERx*2

PWM Center Align Enable Register (PWMCAE)

CAEx — Center Aligned Output Mode on channel x

• 1 = Channel x operates in center-aligned output mode.

• 0 = Channel x operates in left-justified output mode.

2.6 PWM Cascade Register

Two 8-bit PWM channels can be connected into a 16-bit PWM channel, as shown below:

The number of cascaded PWM channels and corresponding registers are as follows:

PWM Control Register (PWMCTL) Cascade Control Register

CONxy——Concatenate channels x and y

• 1 = Channels x and y are connected as one 16-bit PWM channel.

• 0 = Channels x and y are two independent 8-bit PWMs.

3. PWM Configuration Example

Configure PWM. Generally, follow the following 6 steps to configure the registers in ().

• Disable PWM (PWME)

• Select PWM clock, prescaler and divider (PWMPRCLK, PWMSCLA, PWMSCLB, PWMCLK)

• Select polarity (PWMPOL)

• Select alignment mode (PWMCAE)

• Programming Duty Cycle and Period (PWMDTYx, PWMPERx)

• Enable PWM (PWME)

Initialization subroutine example

void PWM_Init(void)

{

PWME = 0x00; //Disable PWM module

PWMPRCLK = 0x06; //CLOCKA pre-scaling is set to 6

PWMSCLA = 125; //The frequency division factor of SA is set to 125

PWMCLK = 0x01; //Channel 0 selects SA as PWM clock

PWMPER0 = 200; //Channel 0 period register is set to 200

PWMDTY0 = 0; //Channel 0 duty cycle register setting

PWMPOL = 0x01; //PWM output is high level first, then becomes low level

PWMCAE = 0x00; //Left-aligned output

PWMCTL = 0x00; // No cascade

PWME = 0x01; // Enable PWM channel 0

}