Optimization level description (for reference only):
The Code Optimization column is used to set the optimization level of C51. There are 9 optimization levels in total.
level (as written in the book), the high optimization level includes all the previous optimization levels.
The following are explained:
Level 0 optimization:
1. Constant folding: Whenever possible, the compiler performs calculations that convert expressions into constant numbers, where
Including calculation of running address.
2. Simple access optimization: Optimize access to internal data and bit addresses of the 8051 system.
3. Jump optimization: The compiler always defers the jump to the final target, so the command to jump between jumps
is deleted.
Level 1 optimization:
1. Dead code elimination: useless code segments are eliminated.
2. Jump rejection: Based on a test backtrace, conditional jumps are carefully examined to determine whether they can be simplified
or delete.
Level 2 Optimization:
1. Data coverage: Data and bit segments suitable for static coverage are identified and marked. Connecting locator BL51
By analyzing the global data flow, segments that can be statically covered are selected.
3 levels of optimization:
1. "Peephole" optimization: Remove redundant MOV commands, including unnecessary loading of objects from memory and
In addition, if it can save storage space or program execution time, complex operations will be replaced by simple ones.
Replaced by a single operation.
4 levels of optimization:
1. Register variables: Keep automatic variables and function parameters in working registers whenever possible.
No data memory space will be reserved for these variables.
2. Extended access optimization: variables from IDATA, XDATA, PDATA and CODE areas are directly included
The byte is included in the operation, so most of the time it is not necessary to load it into an intermediate register.
3. Local common sub-expression elimination: If there is a repeated calculation in the expression, the result of the first calculation is
The results are saved and, whenever possible, used in subsequent calculations, thus eliminating cumbersome calculations from the code.
4. CASE/SWITCH statement optimization: Optimize the CASE/SWITCH statement as a jump table or jump string.
5 levels of optimization:
1. Global common subexpression elimination: Whenever possible, identical subexpressions within a function are calculated only once.
The result is stored in a register to replace the new calculation.
2. Simple loop optimization: A loop that occupies a section of memory with a constant will be optimized when it is run.
6-level optimization:
1. Loop: If the program code can be executed faster and more efficiently, the program loop will be cycled.
7 levels of optimization:
1. Extended entry optimization: Use DPTR data pointers, pointers and array accesses for register variables when appropriate.
The program code is optimized to reduce size and increase execution speed.
8-level optimization:
1. Common tail merging: When there are multiple calls to the same function, some setup code can be reused.
This reduces the length of program code.
9-level optimization:
1. Common subroutine blocks: detect repeated instruction sequences and convert them into subroutines.
Even the code may be rearranged to get more reusable instruction sequences.
Of course, the higher the optimization level, the better. It should be selected according to specific requirements.
KeilC51 compiler has an optimization setting. Different optimization settings will produce different compilation results.
Generally, the default compilation optimization setting is set to level 8 optimization, and the actual maximum optimization setting can be set to level 9 optimization:
1. Dead code elimination.
2.Data overlaying.
3.Peephole optimization.
4.Register variables.
5.Common subexpression elimination.
6.Loop rotation.
7.Extended Index Access Optimizing.
8.Reuse Common Entry Code.
9. Common Block Subroutines.
Appendix: Optimization levels and optimization effect levels in Keil C51
0 Constant folding: The compiler pre-computes the result and replaces the expression with a constant whenever possible. This includes running
Address calculation.
Optimizing simple accesses: The compiler optimizes accesses to internal data and bit addresses of the 8051 system.
Jump optimization: The compiler always expands jumps to the final target, and multi-level jump instructions are removed.
1 Dead code removal: useless code segments are deleted.
Reject Jumps: Closely examine conditional jumps to determine if they can be improved or removed by inverting the test logic.
2 Data coverage: Data and bit segments suitable for static coverage are determined and internally marked.
The connector/locator can select the segments that can be covered through global data flow analysis.
3 Peephole optimization: Eliminate redundant MOV instructions. This includes unnecessary loads from storage and constants.
Replace complex operations with simpler ones when storage space or execution time can be saved.
4 Register variables: Automatic variables and function parameters are allocated to registers if possible.
The storage area reserved for variables is omitted.
Optimized extended access: variables of IDATA, XDATA, PDATA and CODE are directly included in the operation.
Most of the time it is not necessary to use the intermediate registers.
Local common subexpression elimination: If an expression is used to perform the same calculation repeatedly, the first occurrence is saved.
The result of the calculation may be used later. The redundant calculation is deleted.
Case/Switch optimization: The code containing SWITCH and CASE is optimized into jump tables or jump queues.
5 Global common sub-expression deletion: The same sub-expression in a function may be calculated only once.
times. Intermediate results are stored in registers and used in a new calculation.
Simple loop optimization: Loop programs that fill memory with a constant are modified and optimized.
6 Loop Optimization: The program optimizes the loop if the resulting program code is faster and more efficient.
7 Extended index access optimization: Use DPTR for register variables when appropriate. For pointer and array access
Optimize for execution speed and code size.
8 Common tail merging: When a function has multiple calls, some setup code can be reused, so
Reduce program size.
9 Common block subroutines: detect loop instruction sequences and convert them into subroutines. Cx51 even rearranges
code to get a larger loop sequence.
Optimization Theory
When it comes to optimization, many people are actually in a dilemma, because in the career of a C51 software engineer, he will always be
KEIL's optimization is a trick once or several times. I have been tricked before, and I believe you who are reading this article have also been tricked before. If you reply
If you answer no, it only means that you haven't written many C51 programs!
Take a look at the optimization level options of KEILC:
There are 10 levels of optimization from 0 to 9, 0 is the lowest, 9 is the highest, for an ordinary program, set the highest and lowest levels
The amount of code after compilation can sometimes vary greatly. For example, the DX board DEMO program has 14K after level 0 optimization.
After level 9 optimization, the CODE is 10K, and the difference is 4K. It can be seen how big the difference is.
In fact, we don't need to know how or what KEIL will optimize your program at each level.
Well, we just need to write and treat your program with a rigorous attitude.
In my opinion, if the program can still run perfectly after 9 levels of optimization, you can understand KEIL's temper.
Okay, let’s get to the point:
Some people are used to selecting the same optimization level for the entire program. In fact, each C file can have its own optimization level.
Chemical level:
Right-click your module (.C) in the workspace and select Options for File xxx. The following interface will appear.
noodle:
In the C51 options, you can select optimization levels and warning levels, etc. C files that have been set independently
There will be special markings:
To remind you that the compilation of this file is not the default setting!
If you think that module optimization is not detailed enough, you can consider local optimization, that is, to implement a certain function.
You can perform a certain level of optimization. When you find that a certain function always becomes abnormal when the 9th level optimization is performed,
If you want other functions and program segments to remain as concise as possible, local optimization can be quite useful.
This function is introduced in the KEIL manual:
#pragma OPTIMIZE(x) x is the optimization level you want, generally used as follows:
#pragma OPTIMIZE(6)
void FunA()
{ }
......
......
#pragma OPTIMIZE(9)
void FunB()
{ }
The above means that all functions from void FunA() to void FunB(), including FunA,
All use level 6 optimization, and from FunB onwards, unless #pragma OPTIMIZE is used, all use level 6 optimization.
Optimized with level 9.
OPTIMIZE can also have one more parameter, speed and size.
Usage: #pragma OPTIMIZE(9,speed) or #pragma OPTIMIZE(5,size)
The corresponding is level 9 optimization, which focuses on speed, or level 5 optimization, which focuses on minimizing space.
In actual use, it was found that the program was written in white during simulation and breakpoints could not be set.
The answer I found is that the optimization level is too high and some common programs are optimized.
I had to lower the optimization level.
Previous article:Three compilation modes in KEIL and their impact on variable space
Next article:Why can't I find absacc.h in the keil software? How can I find it?
Recommended ReadingLatest update time:2024-11-16 10:39
- Popular Resources
- Popular amplifiers
- 西门子S7-12001500 PLC SCL语言编程从入门到精通 (北岛李工)
- Siemens Motion Control Technology and Engineering Applications (Tongxue, edited by Wu Xiaojun)
- How to read electrical control circuit diagrams (Classic best-selling books on electronics and electrical engineering) (Zheng Fengyi)
- MCU C language programming and Proteus simulation technology (Xu Aijun)
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
- Innolux's intelligent steer-by-wire solution makes cars smarter and safer
- 8051 MCU - Parity Check
- How to efficiently balance the sensitivity of tactile sensing interfaces
- What should I do if the servo motor shakes? What causes the servo motor to shake quickly?
- 【Brushless Motor】Analysis of three-phase BLDC motor and sharing of two popular development boards
- Midea Industrial Technology's subsidiaries Clou Electronics and Hekang New Energy jointly appeared at the Munich Battery Energy Storage Exhibition and Solar Energy Exhibition
- Guoxin Sichen | Application of ferroelectric memory PB85RS2MC in power battery management, with a capacity of 2M
- Analysis of common faults of frequency converter
- In a head-on competition with Qualcomm, what kind of cockpit products has Intel come up with?
- Dalian Rongke's all-vanadium liquid flow battery energy storage equipment industrialization project has entered the sprint stage before production
- Allegro MicroSystems Introduces Advanced Magnetic and Inductive Position Sensing Solutions at Electronica 2024
- Car key in the left hand, liveness detection radar in the right hand, UWB is imperative for cars!
- After a decade of rapid development, domestic CIS has entered the market
- Aegis Dagger Battery + Thor EM-i Super Hybrid, Geely New Energy has thrown out two "king bombs"
- A brief discussion on functional safety - fault, error, and failure
- In the smart car 2.0 cycle, these core industry chains are facing major opportunities!
- The United States and Japan are developing new batteries. CATL faces challenges? How should China's new energy battery industry respond?
- Murata launches high-precision 6-axis inertial sensor for automobiles
- Ford patents pre-charge alarm to help save costs and respond to emergencies
- New real-time microcontroller system from Texas Instruments enables smarter processing in automotive and industrial applications
- AD Design Tips
- [ESP32-S2-Kaluga-1 Review] 5. Use LGVL to create a low-level interface?
- Kill TPS54340
- Why is the voltage ringing spike of MOSFET different in boost and buck mode?
- The circuit for discharging the PFC output capacitor is shown in Figure 2.
- Basic syntax of Verilog HDL
- Found a method to import Altium Designer into SIwave
- Thanks to okhxyyo for searching and fish001 for sharing
- Please advise, is it easy to pass the postgraduate examination and graduate, and how useful is the degree certificate?
- About the LAUNCHXL-F28379D Development Kit