Summarize

• P0: Open-drain bidirectional I/O port without built-in pull-up resistor, can be used as a high-impedance input terminal.
  When P0 port is used as a normal I/O, an external 10KΩ pull-up resistor is required. When used as a low 8-bit address/data bus, no external pull-up resistor is required.

• P1 ~ P3: Bidirectional I/O ports with built-in pull-up resistors. Each port buffer can receive and output 4 TTL gate circuits.

• When P0 ~ P3 are used as input terminals, the P0 ~ P3 ports must be set to 1 first, so that the internal field effect tube is cut off, thus not affecting the input level.

• P0 ~ P3 can all be bit-operated.

The following picture is for fun. If you don't have any basic knowledge, this thing looks like self-castration.

1. P0

1 output latch (D-type flip-flop)
2 tri-state buffers (control read pins or read latches)
1 output drive circuit (composed of a pair of field effect transistors FET)
1 output control terminal (composed of an AND gate, an inverter, and a switch MUX)

1.1 Make an input port

The input signal of the P0 port is sent to both the tri-state buffer below and the drain of V2. If the latch is previously latched as 0, that is, Q=0, Q'=1, then V2 is turned on, and the P0 port is clamped at the 0 level through the external pull-up resistor of the P0 port, and 1 cannot be sent to the P0 port. Therefore, before data is input to the P0 port, 1 must be written to the latch through the internal bus, that is, Q=1, V2 is turned off, and the 1 input from the P0 port can be sent to the input of the tri-state gate. At this time, a read control signal (high level) is sent to the read pin of the tri-state gate, and 1 can be sent to the internal bus through the tri-state gate.

1.2 Make output port

At this time, the CPU inside the single-chip microcomputer will send a 0 to the control end of the AND gate. The 0 at the control end closes the AND gate on the one hand, so that the signal sent by the address/data bus cannot pass through the AND gate; on the other hand, it controls the electronic switch to connect the electronic switch to the Q' end of the latch. At this time, if a write pulse signal is sent to the write latch end CP, the data sent by the internal bus can enter the latch through the D end and output from the Q and Q' ends. If the D end inputs 1, the Q' end outputs 0, which turns off the field effect tube V2. Through the external pull-up resistor of the P0 port, the P0 port can output a high level 1.

2. P1

1 output latch
2 tri-state input buffers
Output drive circuit

2.1 Input Function

At this time, Q=0, non-Q=1, the field effect tube is turned on, and through the internal pull-up resistor of P1 port, P1 port is clamped at 0 level, and 1 cannot be sent to P1 port. So like P0 port, before data is input to P1 port, 1 must be written to the latch through the internal bus to make non-Q=0, the field effect tube is turned off, and the 1 input from P1 port can be sent to the input end of the input tri-state buffer. At this time, a read control signal is sent to the read pin of the tri-state gate, and 1 can be sent to the internal bus through the tri-state buffer.

2.2 Output Function

First send a write pulse signal to the CP end of the latch, and the data sent by the internal bus can enter the latch through the D end and be output from the Q and non-Q ends. If DUAN input is 1, non-Q = 0, 0 is sent to the gate of the field effect tube, the field effect tube is cut off, and 1 is output from P1.

3. P2

1 output latch
1 switch MUX
2 three-state input buffers
1 inverter
Output drive circuit

3.3 Input Function

Similarly, it is necessary to write 1 to the latch through the internal bus first, so that Q=1, the field effect tube is turned off, and the 1 input from the P2 pin can be sent to the input end of the three-state gate. At this time, send a read control signal to the read pin, and 1 can be sent to the internal bus through the three-state gate.

3.2 Output Function

At this time, a write pulse signal is sent to the CP end of the latch, and the data on the internal bus is latched into the latch and output from the Q end, and then output from the P2 port through the MUX switch, NOT gate and field effect transistor.

4. P3

1 output latch
3 input buffers
Output drive circuit (including 1 NAND gate, 1 field effect transistor T, pull-up resistor R)

4.1 Input and Output

The usage is similar to P1 and P2.

4.2 Multiplexing Function

At this time, the port can input the interrupt request signal sent by the external device.