Design of adaptive Ethernet communication interface for LPC23xx

The Ethernet interface is the hardware foundation for Ethernet communication in embedded systems. With the advancement of microelectronics technology, many embedded control chips have integrated Ethernet controllers, which makes the development of Ethernet interfaces in embedded systems more convenient. LPC23xx is a microcontroller based on the ARM7TDMIS core launched by NXP Semiconductors (created by Philips) around December 2006. Compared with LPC21xx and LPC22xx, the most prominent feature is the on-chip integration of 10Mbps/100Mbps Ethernet controller.

1 Structure and configuration of LPC23xx Ethernet controller

As shown in Figure 1, the functions of the main parts of the LPC23xx Ethernet interface are as follows:

Figure 1 Schematic diagram of the LPC23xx Ethernet interface

① Control register, used to configure the working mode of Ethernet controller, read the current state of the controller, etc.;
② Bus interface, the interface for data exchange between AHB bus and Ethernet controller;
③ Receive/transmit DMA, realize bulk data transmission from receive/transmit buffer to bus interface;
④ Receive/transmit buffer, work with DMA to temporarily store received/transmitted data;
⑤ Transmit flow control, insert Ethernet pause frame to control network flow when network load is too large;
⑥ Receive filter, filter out the control part of Ethernet frame and extract valid data;
⑦ MII (Media Independent Interface)/RMII (Reduced Media Independent Interface), interface for real-time data communication with external PHY device according to specified timing;
⑧ MMII (MII Management Interface), configure the working mode of PHY device and read the current state information of PHY device.

Before using the Ethernet controller of LPC23xx, users must write the correct configuration information into the control register in Figure 1. The steps are as follows:

① Clear the software reset state of the LPC23xx Ethernet controller;
② Correctly configure the PHY device through MMII;
③ Select the communication interface (RMII or MII) with the PHY device. Due to the chip size, NXP's LPC 2364, LPC2366, LPC2368 and LPC2378 only have RMII pins;
④ Configure the DMA engine and the first address and length of the receive/send buffer;
⑤ Configure the MAC (media access control) address of the Ethernet interface and select the Ethernet rate (10 Mbps or 100 Mbps);
⑥ Enable the receive/send channel.

Among the above 6 steps, the configuration of the receive/send buffer (step ④) is more critical. The following is a detailed configuration process. In order not to affect the real-time performance of data transmission on the Ethernet interface, the 16KB RAM dedicated to the LPC23xx Ethernet controller is generally selected as the physical carrier of the receive/send buffer. According to the structure of Ethernet frame, the receive/transmit buffer can be divided into several relatively independent buffer units (or not divided), and each unit corresponds to one or more descriptors and status characters. The descriptor is used to set the first address and control information of the corresponding part, and the status character stores the latest status information of the corresponding unit. These descriptors and status characters logically form a ring array: the first address of the descriptor ring array is specified by RxDescriptor (receive descriptor base address register) / TxDescrip tor (transmit descriptor base address register), and the size is specified by RxDecriptorNumber (receive descriptor register number) / TxDescriptorNumber (transmit descriptor register number); the first address of the status character array is specified by RxStatus (receive status base address register) / TxStatus (transmit status base address register), and the size is the same as the descriptor array. After the descriptor array and status symbol array are formed, the descriptor status symbol array can be operated through RxProducerIndex (receive generation index register)/TxProducerIndex (transmit generation index register) and RxConsumerIndex (receive consumption index register)/TxConsumerIndex (transmit consumption index register) to realize data reception/transmission.

2 Control of network data reception and transmission

NXP has a relatively detailed introduction to the reception and transmission of data in its Ethernet controller in the user guide of LPC23xx (reference [2]); but it does not involve the concept of circular array of descriptors and status symbols. The control process of reception and transmission is relatively mechanical. This paper makes improvements on this based on actual engineering applications. Taking transmission as an example, Figure 2 shows a continuous transmission process. The transmission buffer is divided into 4 units. 0 and 4, 1 and 5, 2 and 6, 3 and 7 are the descriptors corresponding to these 4 units. The sending process is as follows:

① If the last data transmission is completed, the state shown in Figure 2(a) is obtained, and TxProducerIndex=TxConsumerIndex.
② Write the data to be sent into the 4 buffer units, and update TxProduceIndex to 4TxProducerIndex, which is the state shown in Figure 2(b), and the data starts to be sent.
③ Wait for the last transmission to end (waiting can be achieved by interruption or query), and get the state of data transmission completion in Figure 2(c);
④ If there is subsequent data to be sent, write the data into the 4 buffer units again, update TxProducerIndex to 4TxProducerIndex, and get the state shown in Figure 2(d), and the data starts to be sent.
⑤ Repeat the above process to obtain the continuous sending process shown in Figure 2.

Figure 2 Continuous transmission process of LPC23xx Ethernet controller

The receiving and sending processes are similar. If the receiving channel of the LPC23xx controller has been correctly configured, an interrupt will be generated when the four buffer units (assuming that the receiving buffer is also divided into four units) are full. Read these four buffer units in the interrupt service program, and then update RxConsumerIndex to 4RxConsumerIndex to complete a receiving process. It should be pointed out that both the receiving and sending channels of the LPC23xx Ethernet controller need to be "generated" before "consumed". For the receiving channel, the Ethernet controller is the "generator" and the host is the "consumer"; the sending channel is just the opposite.

3 Configuration of PHY Devices

The LPC23xx controller provides RMII and MMII to communicate data with the PHY device. Among them, RMII is responsible for the transmission and reception of network data, and MMII is responsible for the configuration of the PHY device and the reading of the current status. This design selects the National Semiconductor DP83848I chip as the PHY device of the Ethernet interface, and its application circuit is shown in Figure 3. DP83848I can be configured by hardware or software. This design chooses to configure by hardware, and read the latest status of DP83848I through MMII.

The adaptive ability of Ethernet interface is reflected by the auto-negotiation function of DP83848I. The auto-negotiation function provides a mechanism for exchanging configuration information between the two ends of the network connection, under which the two ends will automatically select the optimal configuration.

DP83848I supports 4 different Ethernet working modes (10 Mbps half-duplex, 10 Mbps full-duplex, 100 Mbps half-duplex and 100Mbps full-duplex). The auto-negotiation function automatically selects the highest performance working mode based on the chip configuration. The levels of AN_EN, AN1 and AN0 pins of DP83848I control the auto-negotiation function. During the period when the RESET_N pin inputs a low pulse (reset signal), the levels of AN_EN, AN1 and AN0 are sampled to determine the working mode of the chip. When AN_EN, AN1 and AN0 are all "1", that is, R1, R2 and R3 are connected in Figure 3, the four working modes are within the negotiation range.

The configuration process of LPC23xx for DP83848I is as follows:

① Send a reset signal with a pulse width greater than 1 μs and wait for the auto-negotiation process to complete;
② Query the 5th bit of the basic mode status register (BMSR). When this bit becomes high, it indicates that the auto-negotiation process is completed and the waiting is over;
③ Query bits 15, 14, 13, 12, and 11 of the BMSR to obtain the working mode of the Ethernet interface;
④ Configure the working mode of the LPC23xx Ethernet controller.

Figure 3 Hardware circuit of the PHY device of the Ethernet interface

For how to read and write the internal registers of DP83848I through MMII, please refer to page 149150 of reference [2], which will not be repeated here.

This paper introduces an adaptive Ethernet interface designed based on LPC23xx Ethernet controller and DP83848I as PHY device. It applies the latest electronic devices and electronic technology, provides a reference for the software and hardware design of Ethernet bottom layer in embedded systems, and also provides a hardware platform for the implementation of TCP/IP protocol on embedded systems.