Driver Analysis of S3C2440 NAND FLASH Migration to S3C2410

There are some differences between the NAND FLASH driver of S3C2440A and S3C2410. The main difference is that the NAND FLASH registers of these two ICs are slightly different. Please see the difference between the two below:

1. //

2. // Copyright (c) Microsoft Corporation. All rights reserved.

3. //

4. //

5. // Use of this source code is subject to the terms of the Microsoft end-user

6. // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.

7. // If you did not accept the terms of the EULA, you are not authorized to use

8. // this source code. For a copy of the EULA, please see the LICENSE.RTF on your

9. // install media.

10. //

11. //------------------------------------------------ ----------------------------------

12. //

13. // Header: s3c2410x_nand.h

14. //

15. // Defines the NAND controller CPU register layout and definitions.

16. //

17. #ifndef __S3C2410X_NAND_H

18. #define __S3C2410X_NAND_H

20. #if __cplusplus

21. extern "C"

22. {

23. #endif

26. //------------------------------------------------ ----------------------------------

27. // Type: S3C2410X_NAND_REG

28. //

29. // NAND Flash controller register layout. This register bank is located

30. // by the constant CPU_BASE_REG_XX_NAND in the configuration file

31. // cpu_base_reg_cfg.h.

32. //

34. typedef struct

35. {

36. UINT32 NFCONF; // configuration reg

37. UINT8 NFCMD; // command set reg

38. UINT8 pad1[3]; // pad

39. UINT8 NFADDR; // address set reg

40. UINT8 pad2[3]; // pad

41. UINT8 NFDATA; // data reg

42. UINT8 pad3[3]; // pad

43. UINT32 NFSTAT; // operation status reg

44. UINT32 NFECC; // error correction code 0

46. } S3C2410X_NAND_REG, *PS3C2410X_NAND_REG;

49. #if __cplusplus

50. }

51. #endif

53. #endif

The above code is the register of S3C2410A. Let's take a look at the register address description of S3C2440A:

1. //

2. // Copyright (c) Microsoft Corporation. All rights reserved.

3. //

4. //

5. // Use of this source code is subject to the terms of the Microsoft end-user

6. // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.

7. // If you did not accept the terms of the EULA, you are not authorized to use

8. // this source code. For a copy of the EULA, please see the LICENSE.RTF on your

9. // install media.

10. //

11. //------------------------------------------------ ----------------------------------

12. //

13. // Header: s3c2440a_nand.h

14. //

15. // Defines the NAND controller CPU register layout and definitions.

16. //

17. #ifndef __S3C2440A_NAND_H

18. #define __S3C2440A_NAND_H

20. #if __cplusplus

21. extern "C"

22. {

23. #endif

26. //------------------------------------------------ ----------------------------------

27. // Type: S3C2440A_NAND_REG

28. //

29. // NAND Flash controller register layout. This register bank is located

30. // by the constant CPU_BASE_REG_XX_NAND in the configuration file

31. // cpu_base_reg_cfg.h.

32. //

34. typedef struct

35. {

36. UINT32 NFCONF; // configuration reg

37. UINT32 NFCONT;

38. UINT8 NFCMD; // command set reg

39. UINT8 d0[3];

40. UINT8 NFADDR; // address set reg

41. UINT8 d1[3];

42. UINT8 NFDATA; // data reg

43. UINT8 d2[3];

44. UINT32 NFMECCD0;

45. UINT32 NFMECCD1;

46. UINT32 NFSECCD;

47. UINT32 NFSTAT; // operation status reg

48. UINT32 NFESTAT0;

49. UINT32 NFESTAT1;

50. UINT32 NFMECC0; // error correction code 0

51. UINT32 NFMECC1; // error correction code 1

52. UINT32 NFSECC;

53. UINT32 NFSBLK;

54. UINT32 NFEBLK; // error correction code 2

56. } S3C2440A_NAND_REG, *PS3C2440A_NAND_REG;

59. #if __cplusplus

60. }

61. #endif

63. #endif

The difference between the two is huge. Therefore, the difficulty in transplantation is mainly the ECC part. At the same time, the addresses of some register bits are different and need to be modified, as shown below:

1. // Use Macros here to avoid extra over head for c function calls

2. #define READ_REGISTER_BYTE(p) (*(PBYTE)(p))

3. #define WRITE_REGISTER_BYTE(p, v) (*(PBYTE)(p)) = (v)

4. #define READ_REGISTER_USHORT(p) (*(PUSHORT)(p))

5. #define WRITE_REGISTER_USHORT(p, v) (*(PUSHORT)(p)) = (v)

6. #define READ_REGISTER_ULONG(p) (*(PULONG)(p))

7. #define WRITE_REGISTER_ULONG(p, v) (*(PULONG)(p)) = (v)

The above code can be used for both S3C2410 and S3C2440. When I transplanted them, the two parts were the same. Of course, the registers of S3C2443 and S3C2450 have not changed much, but the NAND FLASH driver in the BSP of S3C2450 has changed a lot. I will analyze it later. Now I will analyze this under WINCE5.0. I haven't had time to transplant WINCE6.0 yet. I usually like to transplant it myself, so that I can have a deeper understanding of the WINCE process and become more familiar with this IC. Let's take a look at the difference between the two.

Register macro definition of S3C2440A:

1. //MACROS

2. #define NF_CE_L() WRITE_REGISTER_USHORT(pNFCONT, (USHORT) (READ_REGISTER_USHORT(pNFCONT) & ~(1<<1)))

3. #define NF_CE_H() WRITE_REGISTER_USHORT(pNFCONT, (USHORT) (READ_REGISTER_USHORT(pNFCONT) | (1<<1)))

4. #define NF_CMD(cmd) WRITE_REGISTER_USHORT(pNFCMD, (USHORT) (cmd))

5. #define NF_ADDR(addr) WRITE_REGISTER_USHORT(pNFADDR, (USHORT) (addr))

6. #define NF_DATA_R() READ_REGISTER_BYTE(pNFDATA)

7. #define NF_DATA_W(val) WRITE_REGISTER_BYTE(pNFDATA, (BYTE) (val))

8. #define NF_DATA_R4() READ_REGISTER_ULONG(pNFDATA)

9. #define NF_DATA_W4(val) WRITE_REGISTER_ULONG(pNFDATA, (ULONG) (val))

10. #define NF_STAT() READ_REGISTER_USHORT(pNFSTAT)

11. #define NF_MECC_UnLock() WRITE_REGISTER_USHORT(pNFCONT, (USHORT) (READ_REGISTER_USHORT(pNFCONT) & ~(1<<5)))

12. #define NF_MECC_Lock() WRITE_REGISTER_USHORT(pNFCONT, (USHORT) (READ_REGISTER_USHORT(pNFCONT) | (1<<5)))

13. #define NF_RSTECC() WRITE_REGISTER_USHORT(pNFCONT, (USHORT) (READ_REGISTER_USHORT(pNFCONT) | (1<<4)))

14. #define NF_WAITRB() {while(!(NF_STAT() & ​​(1<<1))) ;}

15. #define NF_CLEAR_RB() WRITE_REGISTER_USHORT(pNFSTAT, (USHORT) (READ_REGISTER_USHORT(pNFSTAT) | (1<<2)))

16. #define NF_DETECT_RB() {while(!(NF_STAT() & ​​(1<<2)));}

17. #define NF_ECC() READ_REGISTER_ULONG(pNFECC)

Register macro definition of S3C2410A:

1. //MACROS

2. #define NF_CE_L() WRITE_REGISTER_USHORT(pNFCONF, (USHORT) (READ_REGISTER_USHORT(pNFCONF) & ~(1 << 11)))

3. #define NF_CE_H() WRITE_REGISTER_USHORT(pNFCONF, (USHORT) (READ_REGISTER_USHORT(pNFCONF) | (1 << 11)))

4. #define NF_CMD(cmd) WRITE_REGISTER_USHORT(pNFCMD, (USHORT) (cmd))

5. #define NF_ADDR(addr) WRITE_REGISTER_USHORT(pNFADDR, (USHORT) (addr))

6. #define NF_DATA_R() READ_REGISTER_USHORT(pNFDATA)

7. #define NF_DATA_W(val) WRITE_REGISTER_BYTE(pNFDATA, (BYTE)(val))

9. #define NF_STAT() READ_REGISTER_USHORT(pNFSTAT)

11. #define NF_RSTECC() WRITE_REGISTER_USHORT(pNFCONF, (USHORT) (READ_REGISTER_USHORT(pNFCONF) | (1 << 12)))

12. #define NF_WAITRB() {while(!(NF_STAT() & ​​(1<<0))) ;}

13. #define NF_DETECT_RB() {while(!(NF_STAT() & ​​0x01));}

14. #define NF_ECC() READ_REGISTER_ULONG(pNFECC)

The registers of S3C2410 are the register definitions that I have modified. The main differences are: NF_CE_L(), NF_CE_H(), NF_RSTECC(), NF_WAITRB(), NF_DETECT_RB(). These registers can be distinguished by the detailed descriptions on the datasheets of the two. I will not explain them in detail here! Modifying the registers is the first and most important step in porting the NAND FLASH driver.