IT8528 memory study notes

IT8528E, this chip integrates multiple peripheral modules, the core is 8032, and uses the 8051 instruction set.

Therefore, this MCU "core" is 51 cores.

You can simply think that this is an 8051 microcontroller with richer peripheral resources. The block diagram is as follows:

IT8528 related memory mainly has three parts:

iRAM: 256Byte of RAM inside the 8032, this part belongs to the 8032 core.

XRAM: 4K RAM outside the core, this part is inside the IT8528 chip.

XROM: External Flash ROM, the size is uncertain, generally 64K--128K, connected through SPI.

Internal RAM

It belongs to the 8032 core part, has fast access speed and small capacity. Logical addresses and SFR registers are multiplexed.

The lower 128 bytes of data memory can be addressed either directly or indirectly.

The upper 128 bytes of RAM and the special function register area share the same address range, both using the 0x80-0xFF address space.

The address spaces overlap, but are physically independent and are distinguished by different addressing methods when used. The upper 128 bytes can only be addressed indirectly, and the special function register area can only be addressed directly.

The lower 128 bytes of RAM are also called general RAM areas. The working register group is 32 bytes from 0x00 to 0x1F, divided into 4 groups of 8 registers, labeled R0 to R7, and they belong to different physical spaces. Using a register bank can increase the speed of operations. The combination of RS1 and RS0 in the program status word PSW register determines the currently used register bank.

It is bit addressable from 0x20 to 0x2F, a total of 16 bytes. It can be addressed by byte like ordinary bytes, or it can be addressed by bit. Bitwise addressing has a total of 128 bits, and the bit addressing range is 0x00-0x7F. It should be noted here that it seems to be the same as the lower 128-byte addressing range of RAM, but there are essential differences between the two. Bit addresses point to a bit, while byte addresses point to a byte, and are distinguished by different instructions in the program.

The internal RAM uses an 8-bit data bus with an addressing range of 256Byte, and the internal RAM operation command is MOV.

External RAM

Although it is located inside IT8528, relative to the 8032 core, it is an external data memory, also called XRAM.

--address space

The range of RAM addresses that the kernel can access is the address space. This range is determined by the data bus. The 8051 core uses a 16-bit data bus for external data memory, that is, the RAM range it can access is 0-64K.

The range that the kernel can access is this range, but in actual practice the physical size of the external RAM may not be 64KByte, or the size available for user programs may not be 64KByte.

The RAM address space is 64K. In actual chip design, different "physical storage" will be mapped.

--Map module register

When using the many peripheral modules inside IT8528, each module requires Data, Status, and Control registers. These registers are mapped to specific RAM addresses and can be accessed after being defined in the software.

The range of this part is 0x1000-0x3000, and the actual physical location is within each module. The mapped physical space cannot be used by users for other purposes.

--Map external memory

0x0000—0x0FFF (4K). The "physical storage" of this part of the space map is the 8032's external data memory XRAM.

This address space is called Scratch RAM in IT8528 and can also be mapped to external ROM memory.

That is, the kernel executes instructions, which can be fetched from external ROM or external RAM.

The 4K RAM memory inside IT8528 is used to store data such as temporary variables and global variables.

As shown in the figure below, the left side is the 64K logical address space, and the right side is the mapped "physical storage".

Simply put, the logical address space is 0-64K, and there may be no corresponding "physical storage" physically mapped to it, or the mapped "physical storage" has been used as a register by other components, and the user program cannot customize it.

The external RAM uses a 16-bit data bus with an addressing range of 64K, and the operating command of the external RAM is MOVX.

External ROM

External ROM, also called external SPI Flash, is used to store program instructions. It is connected to IT8528 through the SPI bus. For 8032, there is no internal ROM and supports external Flash.

Similarly, the 8032 core uses a 16-bit address bus and a 16-bit program counter. The addressable range of program instructions is

0-64KByte. In other words, the program address space is also 0-64KByte.

In fact, IT8528 supports external Flash up to 16M, so there is a problem here. The address bus of the 8032 core is 16bit, and addresses larger than 64K cannot be accessed. How to solve it?

For the 51-core MCU, a storage organization method divided into BANKs is designed to support ROM memory greater than 64K.

The method for dividing the 64K program address space is as follows: (mapping of Flash and 8032 code spaces)

The program address space 0x0000-0x7FFF belongs to the Common Bank and maps "physical storage", that is, the 0x0000-0x7FFF range of Flash.

The program address space 0x8000-0xFFFF belongs to Bank (0-3). The four Banks occupy the same program address space, but the physical intervals in Flash are different.

The address range of CommonBank+Bank_x is exactly 64K, so when 8032 accesses the external address space, it can only access a certain Bank range at the same time. If the compiled function is in another bank, when a cross-bank function call occurs, the bank will be automatically switched. In fact, cutting the Bank is completed by a piece of code generated by the Keil compiler.

For the bank-related registers of IT8528, please refer to its Datasheet.

Through the link file, you can specify a certain function code or a certain piece of data to be placed in a specified Bank.

The external ROM uses a 16-bit address bus with an addressing range of 64K, and the data operation instructions in the external ROM are MOVC.

IT8528 firmware update principle

As can be seen from the above, every instruction executed by the IT8528 core is read from the external SPI Flash in real time.

Conflicts occur when SPI Flash needs to be updated.

At this time, the XRAM memory can be mapped to the code address space, so that the 8032 core will only access XRAM when fetching instructions, instead of accessing the SPI Flash.

The XRAM memory (Scratch RAM) inside IT8528 is 4K in total, numbered 0--4 respectively. The size of each block is as shown in the figure below.

4K of XRAM is always mapped to data space. When needed, configure the code space mapping register to enable, and XRAM will be mapped to the code space.

That is to say, at the same time, Scratch SRAM may be mapped to both data space and code space. Mapping to data space is called Scratch RAM, and mapping to code space is called Scratch ROM.

As shown in the figure below, the location of each block mapped to the code space is configured by the three registers SCARxH/M/L.

The following is a schematic diagram of code space mapping XRAM and SPI Flash.

In order to be compatible with the design IT8528, a register FBCFG is added to complete a fast mapping.

That is, quickly map Scratch SRAM-0 to the F800--FFFF position of the code space.

With the above mapping relationship, the problem of conflict between updating SPI Flash and 8032 fetching instructions is solved.

As shown in the picture below, IT8528 has designed a SMFI module to allow 8032 to access the external SPI Flash.

The principle of accessing IT8528 plug-in SPI Flash through the Host is as shown below.

Update firmware process

The first step is to copy the control function for updating SPI Flash (limited to 256 bytes) to the specified location in SRAM.

Why should we copy the update function to SRAM 0x600 location?

It can be seen from the FBCFG register that setting BIT7 can map Scratch SRAM-0 to 0xF800--0xFFFF.

That is, the 0x000--0x800 part of XRAM is mapped to 0xF800--0xFFFF of the code space.

Therefore, 0x600--0x6FF of XRAM is mapped to 0xFE00--0xFEFF of code space.

The update function is forced to be placed at 0xFE00 through the link script. When this function is called, the instruction fetching position is

0xFE00.

Because the code space 0xFE00--0xFEFF maps 0x600--0x6FF of XRAM.

Therefore, you only need to copy the update function to 0x600--0x6FF of XRAM.

Note: The code of the update function cannot exceed 256Byte.

The second step is to configure the FBCFG register and map Scratch SRAM-0 to the code space.

The third step is to jump to the update function.

The fourth step is to cyclically process the data and instructions of the 6266 or 686C interface in the update function to control the SMFI module to access the SPI Flash.

The above steps are all controlled by UpdateTool under UEFI or OS.

For IT8987, there is internal Flash. In fact, for the 8032 core, it still belongs to external Flash. The so-called internal Flash is just "sealed" inside the chip.

In addition, for the IT557x series of chips, a separate storage space (about 1K) is designed internally for temporary instruction fetching by the core 8032. The above method of copying the update function to XRAM does not need to be used.

Instead, DMA is used to copy the update function to the "hidden storage space" and then execute it.