8051 microcontroller interrupt system structure and interrupt control principle

When several interrupt sources request interrupts from the CPU at the same time, they are queued according to the priority of the real-time events that occur, and the interrupt requests for the most urgent events are processed first, so the microcontroller specifies the priority level of each interrupt source.

When the CPU is processing an interrupt request and another interrupt request with a higher priority occurs, the CPU temporarily stops processing the previous interrupt and instead processes the interrupt request with a higher priority. After processing, the CPU continues execution. In the original interrupt handler, such a process is called interrupt nesting, and such an interrupt system is called a multi-level interrupt system.

Since external asynchronous events interrupt the program being executed by the CPU randomly, when the CPU turns to execute the interrupt service routine, in addition to the hardware automatically pushing the power-off address, that is, the value of the 16-bit PC program counter into the stack, the user must also pay attention Protect information about working registers, accumulators, flag bits, etc. This process is usually called protecting the scene. In order to restore the contents of the original working register, accumulator, flag bits, etc. after completing the interrupt service routine, this process is called restoring the scene; finally, the interrupt return instruction is executed, the power is automatically ejected to the PC, and the main program is returned to continue executing the interrupted program. program.

Let's take a look at the 8051 interrupt system structure and interrupt control:

The 8051 microcontroller has five interrupt request sources and four interrupt control registers IE.IP.TCON and SCON, which are used to control the type of interrupt, interrupt enable, interrupt start and stop, and the priority level of various interrupt sources.

The five interrupt sources have two priority levels. Each interrupt source can be programmed as a high-priority or low-priority interrupt, and two-level interrupt service routine nesting can be achieved. The interrupt sources of 8051 include: external interrupt sources input by INT0 and INT1 pins; three internal interrupt sources, namely the overflow interrupt source of timer T0, the overflow interrupt source of timer T1 and the transmit/receive interrupt source of the serial port. .

The two external interrupt sources input from the INT0 and INT1 pins and their trigger mode control bits are latched in the lower four bits of the special function register TCON. The format is as follows:

IE1, that is, TCON.3: external interrupt INT1 request flag. When the CPU detects an external interrupt signal appearing on the INT1 pin, the hardware sets IE1=1 to request an interrupt. After the CPU executes the interrupt service routine, the IE1 bit is automatically cleared to 0 by the hardware.

IT1, TCON.2: External interrupt INT1 request type, trigger mode control bit, set to 1 or cleared to 0 by software to control the trigger type of external interrupt 1.

IT1=0, external interrupt 1 is set to level trigger mode. When pin INT1 inputs low level, IE1 is set to request an interrupt. The CPU samples the input level of INT1 during S5P2 of each machine cycle. When the low level is sampled, IE1=1 is set. When using the level trigger mode, the external interrupt source input to pin INT1 must remain active until the program is responded to by the CPU. At the same time, before the interrupt service routine is executed, the effective level of the external interrupt source must be canceled, otherwise another interrupt will be generated.

IT1=1, external interrupt 1 is set to edge trigger mode, and the CPU samples the level of pin INT1 in each machine cycle. If in two consecutive samplings, the pin INT1 is sampled to be high level in one cycle, and then the pin INT1 is sampled to be low level in the next cycle, INE1 is automatically cleared to 0 by the hardware. Because an external interrupt is sampled every machine cycle Input level, the high level and low level time of the external interrupt source input must be maintained for more than 12 oscillation cycles to ensure that the CPU detects the negative transition signal, that is, the falling edge.

IEO, TCON.1: external interrupt request flag. When IE0=1, external interrupt 0 requests an interrupt from the CPU. When the CPU responds to the external interrupt, IE0 is cleared to 0 by hardware.

ITO, TCON.0: External interrupt 0 trigger mode control bit. IT0=0, external interrupt 0 is set to edge trigger mode. When IT0=1, external interrupt 0 is set to edge level mode. Its function is similar to IT1.

Interrupt control: In addition to some bits in the special function registers TCON and SCON related to interrupts, there are two special function registers IE and IP dedicated to interrupt control.

Interrupt enabled IE:

In the 8051 microcontroller, the special function register IE bit is the interrupt enable register, which controls whether the CPU generally allows or disables interrupt sources and whether each interrupt source allows interrupts. Its format is:

EA: Interrupt total enable bit. EA=1, the CPU allows interrupts; EA=0, the CPU disables all interrupt requests.

ES: Serial interrupt enable bit. ES=1, serial port interrupt is enabled; ES=0, serial port interrupt is disabled.

EX1: T0 overflow interrupt enable bit. ET0=1, enable T0 interrupt; ET0=0, disable T0 interrupt.

EX0: External interrupt enable bit. EX0=1, enable external interrupt 0 interrupt; EX0=0, disable external interrupt 0 interrupt.

After the 8051 system is reset, all bits in IE are cleared to 0, that is, all interrupts are disabled.

Interrupt priority setting register IP. The 8051 microcontroller has two interrupt priority levels. Each interrupt source can be programmed as a high-priority interrupt or a low-priority interrupt, and can realize two-level interrupt nesting. High-priority interrupt sources can interrupt the execution of low-priority interrupt service routines.

Interrupt sources of the same level or lower priority cannot interrupt the executing interrupt program. To this end, in the 8051 interrupt system, there are two internal priority status flip-flops, which respectively indicate whether the CPU is executing a high-priority or low-priority interrupt service routine, thereby respectively shielding all interrupt applications and other interrupt requests at the same level. Interrupt source request.

The special function register IP is the interrupt priority register.

The control bits of the priority of each interrupt source can be set by the user through software. Its format is as follows:

PS: Serial interrupt priority control bit. PS=1, sets the serial port as a high-priority interrupt; PS=0, sets the serial port as a low-priority interrupt.

PT1: T1 interrupt priority control bit. PT1=1, set timer T1 as a high-priority interrupt; PT=0, set a low-priority interrupt.

TX1: External interrupt 1 interrupt priority level control bit. PX1=1 sets external interrupt 1 as a high-priority interrupt; PC1=0, sets a low-priority interrupt.

PT1: T1 interrupt priority control bit. PT1=1, set timer T1 as a high-priority interrupt; PT1=0, set a low-priority interrupt.

PT0: T0 interrupt priority control bit. PT1=1, set timer T0 as a high-priority interrupt; PT0=0, set a low-priority interrupt.

PX0: External interrupt interrupt priority control bit. PX0=1, set INT1 as high priority. PX0=0, low priority.

After the 8051 is reset, the lower five bits of IP are all cleared to 0, and all interrupt sources are set to low-priority interrupts.

If several interrupt sources with the same priority apply for interrupts from the CPU at the same time, which application is serviced depends on their automatically registered queue numbers within the CPU. The CPU queries the registration number through internal hardware and determines which interrupt request should be responded to first based on natural priority. The natural priorities in order from high to low are: external interrupt 0, timer 0, external interrupt 1, timer 1, and serial interrupt.