Four sets of I/O ports of 8051 microcontroller

1 Overview

The I/O port of the microcontroller is the channel for input signals and output signals. The 8051 microcontroller has four groups of I/O ports, P0, P1, P2, and P3, and each group of ports has 8 pins.

2.P0 port

2.1 Overview

The P0 port has a total of 8 pins P0.0~P0.7. In addition to being used as input pins and output pins, these pins can also be used as address/data bus pins when external memory is connected. The internal circuit structure of each pin of the P0 port is the same, and its internal circuit structure is shown in Figure 1.

Figure 1 Internal circuit structure diagram of P0 port

2.2 Working principle of P0 port used as output port

The following explains that the microcontroller needs to output a high level "1" from the P0.x pin. As shown in Figure 1, the relevant circuit inside the microcontroller sends "0 (low level)" to an input end of the AND gate and the control end of the electronic switch through the control line. On the one hand, the "0" on the control line makes the AND gate close ( That is, when one end of the AND gate is "0", no matter what signal is input to the other end, the output is "0"), the gate of the transistor VT1 is "0" and is cut off, and the signal sent from the address/data line cannot pass through the AND gate and The "0" on the control line of transistor VT1; on the other hand controls the electronic switch, allowing the electronic switch to be connected to the terminal of the latch. The CPU then sends a high level "1" from the internal bus to the D terminal of the latch, and at the same time sends a write latch signal to the CL terminal of the latch. The "1" on the D terminal is immediately stored in the latch and is transferred from Q and terminal outputs, D terminal inputs "1", Q terminal outputs "1", terminal Q terminal outputs "0", terminal output "0" is sent to the gate of transistor VT2 through the electronic switch, VT2 is cut off, since VT1 is also cut off, P0 The .x pin is in a floating state, so a pull-up resistor needs to be connected to the P0.x pin. When VT2 is cut off, the P0.x pin outputs a high level.

The following explains that the microcontroller needs to output a high level "0" from the P0.x pin. As shown in Figure 1, the relevant circuit inside the microcontroller sends "0 (low level)" to an input end of the AND gate and the control end of the electronic switch through the control line. On the one hand, the "0" on the control line makes the AND gate close ( That is, when one end of the AND gate is "0", no matter what signal is input to the other end, the output is "0"), the gate of the transistor VT1 is "0" and is cut off, and the signal sent from the address/data line cannot pass through the AND gate and The "0" on the control line of transistor VT1; on the other hand controls the electronic switch, allowing the electronic switch to be connected to the terminal of the latch. The CPU then sends a high level "0" from the internal bus to the D terminal of the latch, and at the same time sends a write latch signal to the CL terminal of the latch. The "0" on the D terminal is immediately stored in the latch and is transferred from Q and terminal outputs, D terminal inputs "0", Q terminal outputs "0", terminal Q terminal outputs "1", terminal output "1" is sent to the gate of transistor VT2 through the electronic switch, VT2 is turned on, because VT1 is cut off, P0 The .x pin is in a floating state, so a pull-up resistor needs to be connected to the P0.x pin. When VT2 is turned on, the P0.x pin outputs a low level.

In general, when the microcontroller needs to use the P0 port as an output port, the internal CPU will send the control signal "0" to the AND gate and electronic switch, and the AND gate is closed (the upper transistor VT1 is cut off at the same time, connecting the address/data line with the output circuit is separated), the electronic switch connects the latch to the output circuit, and then the CPU sends data and write latch signals to the P0 port latch through the internal bus, and the data passes through the latch, electronic switch and output circuit from the P0 port pin output. When the P0 port is used as an output port, the upper transistor of the internal output circuit is turned off (open circuit), and the drain of the lower transistor is in an open circuit state (called transistor open drain). Therefore, an external pull-up resistor needs to be connected to the P0 port pin. Otherwise "1" or "0" cannot be output reliably.

2.3 Working principle of P0 port used as input port

As shown in Figure 1, when the microcontroller needs to use the P0 port as an input port, the internal CPU will first write "1" to the P0 port latch (send "1" to the D end of the latch and send "1" to the CL end at the same time. Write latch signal), let VT2 cut off and close the output circuit. The signal input by the P0 port pin is sent to the input terminal of the input tri-state gate. At this time, the CPU sends the read pin control signal to the control terminal of the tri-state gate. When the input tri-state gate is opened, the signal input by the P0 port pin can be sent to the internal bus through a tri-state gate.

If the CPU of the microcontroller needs to read the value of the P0 port latch (or read the data stored in the latch), it will send the read latch control signal to the three-state gate (the upper three-state gate). The three-state gate Open, the value of the P0 latch (Q value) is sent to the internal bus through the tri-state gate.

2.4 Working principle of P0 port as address/data bus

As shown in Figure 1, if the P0 port is to be used as an address/data bus, the relevant circuit inside the microcontroller will send a "1" through the control line to open the AND gate and connect the electronic switch to the NOT gate output. When the internal address/data line is "1", "1" is sent to the gate of VT1 through the AND gate on the one hand. VT1 is turned on. On the other hand, it is sent to the NOT gate. After inversion, it becomes "0". The switch is sent to the gate of VT2, VT2 is turned off, VT1 is turned on, and the P0 port pin outputs "1"; when the internal address/data line is "0", VT1 is turned off, VT2 is turned on, and the P0 port pin outputs " 0".

In general, when the microcontroller needs to use the P0 port as an address/data bus, the CPU will send "1" to the control end of the AND gate and the electronic switch, open the AND gate, and connect the internal address/data line to the upper end of the output circuit. Transistor VT1 is turned on, and the electronic switch cuts off the connection between the output circuit and the latch. At the same time, the internal address/data line is inverted through the NOT gate and connected to the lower transistor VT1 of the output circuit. In this way, the states of VT1 and VT2 are reversed, allowing the P0 port to The pin can stably output data or address signals (1 or 0).

3.P1 port

3.1 Overview

The P1 port has a total of 8 pins P1.0~P1.7, which can be used as input pins and output pins. The internal circuit structure of each pin of the P1 port is the same, and its internal circuit structure is shown in Figure 2. The structure of the P1 port is much simpler than that of the P0 port. Its output circuit uses a transistor, and an internal pull-up resistor is connected to the drain of the transistor, so the pull-up resistor does not need to be connected to the external pin of the P1 port.

Figure 2 Internal structure circuit diagram of P1 port

3.2 Working principle of P1 port used as output port

As shown in Figure 2, when the P1 port needs to be used as an output port, the relevant circuit inside the microcontroller will not only send data to the D terminal of the latch, but also send a write latch signal to the CL terminal of the latch. The data sent from the internal bus enters the latch through the D terminal and is output from the Q and terminals. When the D terminal inputs "1", the terminal outputs "0" (the Q terminal outputs "1"), and the "0" on the terminal is sent to the transistor. gate, the transistor is turned off, and "1" is output from the P1 port pin. When the D terminal inputs "0", the terminal outputs "1" (the Q terminal outputs "0"). The "1" on the terminal is sent to the gate of the transistor. The transistor is turned on and "0" is output from the P1 port pin.

3.3 Working principle of P1 port used as input port

As shown in Figure 2, when the P1 port needs to be used as an input port, the relevant circuit inside the microcontroller will first write "1" to the P1 latch, let Q=1, which will cause the transistor to cut off and close the output circuit of the P1 port. , then the CPU sends a read pin control signal to the input tri-state gate control end, the input tri-state gate opens, and the signal input from the P1 port pin is sent to the internal bus through the input tri-state gate.

4.P2 port

4.1 Overview

The P2 port has a total of 8 pins P2.0 ~ P2.7. In addition to being used as input pins and output pins, these pins can also be used as address bus (high 8-bit) pins when external memory is connected. . The internal circuit structure of each pin of the P2 port is the same, and its internal circuit structure is shown in Figure 3.

Figure 3 P2 port internal structure circuit diagram

4.2 Working principle of P2 port used as output port

As shown in Figure 3, when the P2 port needs to be used as an I/O port, the relevant circuit inside the microcontroller will send a control signal to the control end of the electronic switch, allowing the electronic switch to connect to the Q end of the P2 latch. If the P2 port is used as an output port, the CPU will send the data to the D terminal of the latch through the internal bus, and at the same time send a write latch signal to the CL terminal of the latch, and the D terminal data is stored in the latch and It is output from the Q terminal, and then output from the P2 port pin through electronic switches, NOT gates and transistors.

4.3 Working principle of P2 port used as input port