DDR3 configuration process of HI3531

DDR3 initialization configuration process

After the system is powered on, the DDR3 SDRAM initialization operation must be completed before the system can access the DDR3
SDRAM. You need to pay attention to the following points before initializing:

When powering on DDR3 SDRAM, JEDEC standards need to be followed. That is, VDD is provided first,
then VDDQ, and finally VREF and VTT.
 This initialization process needs to be performed after the system enters NORMAL mode.
In DDRC 32bit mode, assuming that the storage space
consists of two DDR3 SDRAMs with a capacity of 1Gbit and a data bus width of 16bit, the initialization steps of DDRC are as follows:
1. The software waits for more than 200us.
2. Configure the DDRC_IOCFG register to 0x467 to configure the IO working mode, matching resistor and signal
driver .
3. Configure the DDRC_RNKCFG register to 0x122 according to the single-chip capacity of the device. The bus address mapping mode is RB-
C-DW mode, the AP is A10, the column address width is 10, and the row address width is 13.
4. Configure DDRC_PHYSRST to 0x0,
configure the DDRC_CDLLCFG and DDRC_QDLLCFG0~3 registers to 0x52, and reset the DDR PHY and DLL.
5. The software waits for 50ns.
6. Configure DDRC_PHYSRST to 0x1,
configure the DDRC_CDLLCFG, DDRC_QDLLCFG0~3 registers to 0x56, and cancel the DDR PHY and DLL reset.
7. The software waits for more than 3us.
8. Configure the DDRC_TIMING2 register [taref] to 0x000 to disable automatic refresh.
9. Configure the DDRC_CTRL register to 0x1 and configure the DDR3 SDRAM to exit the reset state.
10. The software waits for more than 500us.
11. Configure the DDRC_SREFCTRL register to 0x0 to exit the self-refresh state.
12. The software waits for more than 1us.
13. According to the operating frequency and device requirements, configure the DDRC_EMRS01 register and DDRC_EMRS23 register
to set the DDR read latency (cas latency), write latency (cas write latency), write recovery latency (write
recovery), and burst length (burst length) , the output drive impedance and input ODT impedance of the DDR device
, etc.
cas latency and DDRC_TIMING1[cl] must be set to the same value.
cas write latency and DDRC_TIMING1[wl] must be set to the same value. The DDRC_EMRS01 register corresponds to the mode register MRS and extended mode register 1 (EMRS1)
of DDR3 SDRAM .
When configuring this register, you only need A15-A0 of the mode register in the DDR3 SDRAM device manual (the actual
valid bits are: A13~A0). There is no need to configure the highest 3 bits A18~A16 register selection bits of the mode register, that is, the bank address.
However, the bank addresses of some DDRn SDRAM manufacturers are: A17~A15.
14. Configure the DDRC_CONFIG0 register to 0x8000_0610 and the DDRC_CONFIG1 register to 0x785 according to the device type and storage space
, indicating that the DDRC is in 32bit DDR3 SDRAM mode.
The power-on reset value of low-power configuration is turned off. During the initialization process, the low-power automatic entry function and the clock automatic
shut-off However, in normal use, it is recommended to enable low-power control to reduce power consumption. .
15. Configure the storage space base address register DDRC_BASEADDR to 0x8000_0000.
16. Configure the values ​​of DDRC_TIMING0~DDRC_TIMING3 according to the operating frequency and device requirements, where the cl and wl
values ​​must be consistent with the configurations in the DDRC_EMRS01 and DDRC_EMRS23 mode registers.
17. Configure the DDRC_DTRCTRL register to 0x0F00_0503 to enable initialization of automatic training mode.
18. Configure the DDRC_ODTCFG register DDRC_ODTCFG[wodt0]=0x1,
DDRC_ODTCFG[rodt0]=0x0.
19. Configure DDRC_PHYCFG register 0x2.
20. Set the DDRC_INITCTRL register to 0x1 to start the initialization process.
21. Wait for the value of the DDRC_INITCTRL register to become 0 and the initialization is completed.
----End
After completing the above steps, DDR3 SDRAM can work normally.