U-Boot transplantation on FL2440 (1)----Modify the system clock

<1>U-boot source code structure

      The picture comes from Wei Dongshan's "Complete Manual of Embedded Linux Application Development"

       U-boot download address:

<2>U-boot transplantation

    1. Create a new directory and file for the fl2440 development board

      ① Create a new fl2440 directory in the board directory, copy the files in the smdk2410 directory to the fl2440 directory, and rename board/fl2440/smdk2410.c to fl2440.c

      ②Modify the Makefile in the u-boot-1.1.6 directory

smdk2410_config : unconfig

@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0

add after

fl2410_config : unconfig

@$(MKCONFIG) $(@:_config=) arm arm920t fl2410 NULL s3c24x0

Then modify it in board/fl2440/Makefile

COBJS := smdk2410.o flash.o 为 COBJS := fl2440.o flash.o

2. Modify the configuration of SDRAM

① Modify line 126 in the board/fl2440/lowlevel_init.s file

#define REFCNT    0x4f4

②

Modify the board_init function in board/fl2440/fl2440.c, that is, replace the entire function board_init including all its statements.

#define S3C2440_MPLL_400MHZ ((0x7f<<12)|(0x02<<4)|(0x01))

#define S3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02))

#define S3C2440_CLKDIV 0x05

#define S3C2410_MPLL_200MHZ ((0x5c<<12)|(0x04<<4)|(0x00))

#define S3C2410_UPLL_48MHZ ((0x28<<12)|(0x01<<4)|(0x02))

#define S3C2410_CLKDIV 0x03

int board_init (void)

{

S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

gpio->GPACON = 0x007FFFFF;

gpio->GPBCON = 0x00044555;

gpio->GPBUP = 0x000007FF;

gpio->GPCCON = 0xAAAAAAAA;

gpio->GPCUP = 0x0000FFFF;

gpio->GPDCON = 0xAAAAAAAA;

gpio->GPDUP = 0x0000FFFF;

gpio->GPECON = 0xAAAAAAAA;

gpio->GPEUP = 0x0000FFFF;

gpio->GPFCON = 0x000055AA;

gpio->GPFUP = 0x000000FF;

gpio->GPGCON = 0xFF95FFBA;

gpio->GPGUP = 0x0000FFFF;

gpio->GPHCON = 0x002AFAAA;

gpio->GPHUP = 0x000007FF;

if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))

{

clk_power->CLKDIVN = S3C2410_CLKDIV;

__asm__( "mrc p15, 0, r1, c1, c0, 0n"

"orr r1, r1, #0xc0000000n"

"mcr p15, 0, r1, c1, c0, 0n"

:::"r1"

);

clk_power->LOCKTIME = 0xFFFFFF;

clk_power->MPLLCON = S3C2410_MPLL_200MHZ;

delay (4000);

clk_power->UPLLCON = S3C2410_UPLL_48MHZ;

delay (8000);

gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;

}

else

{

clk_power->CLKDIVN = S3C2440_CLKDIV;

__asm__( "mrc p15, 0, r1, c1, c0, 0n"

"orr r1, r1, #0xc0000000n"

"mcr p15, 0, r1, c1, c0, 0n"

:::"r1"

);

clk_power->LOCKTIME = 0xFFFFFF;

clk_power->MPLLCON = S3C2440_MPLL_400MHZ;

delay (4000);

clk_power->UPLLCON = S3C2440_UPLL_48MHZ;

delay (8000);

gd->bd->bi_arch_number = MACH_TYPE_S3C2440;

}

gd->bd->bi_boot_params = 0x30000100;

icache_enable();

dcache_enable();

return 0;

}

③The MPLL and UPLL calculation formulas of S3C2410 and S3C2440 are different, so the get_PLLCLK function also needs to be modified.

Modify in cpu/arm920t/s3c24X0/speed.c:

Modify the get_PLLCLK function:

static ulong get_PLLCLK(int pllreg)

{

S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

head r, m, p, s;

if (pllreg == MPLL)

r = clk_power->MPLLCON;

else if (pllreg == UPLL)

r = clk_power->UPLLCON;

else

hang();

m = ((r & 0xFF000) >> 12) + 8;

p = ((r & 0x003F0) >> 4) + 2;

s = r & 0x3;

if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)

return((CONFIG_SYS_CLK_FREQ * m) / (p << s));

else

return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s));

}

That is, add the above red font under the get_PLLCLK function.

Modify get_HCLK, get_PCLK (paste the code below directly to overwrite these two functions):

#define S3C2440_CLKDIVN_PDIVN (1<<0)

#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)

#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)

#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)

#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)

#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)

#define S3C2440_CLKDIVN_ LK (1<<3)

#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)

#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)

#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)

#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)

#define S3C2440_CAMDIVN_DVSEN (1<<12)

head get_HCLK(void)

{

S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

unsigned long clkdiv;

unsigned long camdiv;

int hdiv = 1;

if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)

return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());

else

{

clkdiv = clk_power->CLKDIVN;

camdiv = clk_power->CAMDIVN;

switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {

case S3C2440_CLKDIVN_HDIVN_1:

hdiv = 1;

break;

case S3C2440_CLKDIVN_HDIVN_2:

hdiv = 2;

break;

case S3C2440_CLKDIVN_HDIVN_4_8:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;

break;

case S3C2440_CLKDIVN_HDIVN_3_6:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;

break;

}

return get_FCLK() / hdiv;

}

}

head get_PCLK(void)

{

S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

unsigned long clkdiv;

unsigned long camdiv;

int hdiv = 1;

if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)

return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());

else

{

clkdiv = clk_power->CLKDIVN;

camdiv = clk_power->CAMDIVN;

switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {

case S3C2440_CLKDIVN_HDIVN_1:

hdiv = 1;

break;

case S3C2440_CLKDIVN_HDIVN_2:

hdiv = 2;

break;

case S3C2440_CLKDIVN_HDIVN_4_8:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;

break;

case S3C2440_CLKDIVN_HDIVN_3_6:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;

break;

}

return get_FCLK() / hdiv / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);

}

}

Re-execute make fl2440_config make all to generate u-boot.bin. Since NAND Flash support has not yet been added, it can be burned into NOR Flash and run.

When making all an error occurs: No CAMDIVN

This must be defined in the include/s3c24x0.h header file, and added to the S3C24X0_CLOCK_POWER structure on line 129: S3C24X0_REG32 CAMDIVN;

Now execute make fl2440_config and make all to generate U-Boot.bin, which can be burned into norflash.