Embedded gateway software and hardware design based on LPC2294 and ENC28J60

With the popularization of the Internet, realizing remote control of smart homes is no longer people’s dream. The so-called remote control refers to the management personnel dialing up remotely through the computer network or both parties accessing the Internet, etc., to connect the computers to be controlled. The desktop environment of the controlled computer is displayed on the own computer, and the remote computer is configured, software installed, modified, etc. through the local computer. Wake-on-remote (WOL), which enables remote booting through the local area network. CAN is the abbreviation of Controller Area Network (CAN). It was developed by the German BOSCH company, which is famous for the development and production of automotive electronic products, and eventually became an international standard (ISO118?8). It is one of the most widely used fieldbuses in the world. In North America and Western Europe, the CAN bus protocol has become the standard bus for automotive computer control systems and embedded industrial control LANs, and has the J1939 protocol, which uses CAN as the underlying protocol and is specially designed for large trucks and heavy industrial machinery vehicles. In recent years, its high reliability and good error detection capabilities have attracted attention, and it is widely used in automotive computer control systems and industrial environments with harsh ambient temperatures, strong electromagnetic radiation, and large vibrations. The network protocol used by CAN and Ethernet is a collection of rules, standards or conventions established for data exchange in computer networks. For example, a microcomputer user communicates with a mainframe operator on the network. Since the two data terminals use different character sets, the commands entered by the operators do not recognize each other. In order to enable communication, it is stipulated that each terminal must first convert the characters in its own character set into the characters in the standard character set before entering the network for transmission. After reaching the destination terminal, it is then converted into the characters in the terminal's character set. Of course, for incompatible terminals, in addition to changing the character set characters. Other characteristics, such as display format, line length, number of lines, screen scrolling method, etc., also need to be changed accordingly.

1 Gateway hardware design

1.1 System hardware structure

The hardware part of the system mainly consists of ARM, Ethernet interface, CAN interface, high-speed memory, JTAG port, reset circuit and power supply. The system hardware structure is shown in Figure 1. ARM transplants the TCP/IP communication protocol and CAN protocol, which can complete the conversion of the Ethernet protocol and the CAN bus protocol, and realize the transparent transmission of communication data between the Ethernet interface and the CAN interface. Ethernet refers to the baseband LAN specification created by Xerox and jointly developed by Xerox, Intel and DEC. It is the most common communication protocol standard used in existing LANs today. Ethernet uses CSMA/CD (Carrier Sense Multiple Access and Collision Detection) technology and runs on multiple types of cables at a rate of 10M/S. Ethernet is similar to the IEEE802·3 series of standards.

1.2 Selection of main controller

The microprocessor uses the 32-bit microcontroller LPC2294 with the ARM7TDMI core of Philips Company. Compared with general microcontrollers, LPC2294 can be embedded in the operating system. LPC2294 has built-in 256 KB of high-speed FLASH memory and 16 KB of static RAM, multiple external interrupts and serial ports. LPC2294 also integrates a CAN controller. As long as a CAN bus transceiver is added, a CAN node can be formed, thus greatly simplifying hardware circuit. A microprocessor is a central processing unit composed of one or a few large-scale integrated circuits. These circuits perform the functions of control components and arithmetic logic components. Compared with traditional central processing units, microprocessors have the advantages of small size, light weight and easy modularization. The basic components of a microprocessor are: register file, arithmetic unit, timing control circuit, and data and address bus. The microprocessor can complete operations such as fetching instructions, executing instructions, and exchanging information with external memory and logic components. It is the computing control part of the microcomputer. It can be combined with memory and peripheral circuit chips to form a microcomputer. Since humans invented the transistor in 1947, semiconductor technology has gone through several generations such as silicon transistors, integrated circuits, very large scale integrated circuits, and very large scale integrated circuits in more than 50 years. The speed of development is unprecedented in other industries. Semiconductor technology has had a wide-ranging impact on the entire society, so it is called the "seed of the industry." The central processing unit refers to the component inside the computer that processes data and controls the processing process. With the rapid development of large-scale integrated circuit technology, chip integration density is getting higher and higher, and the CPU can be integrated on a semiconductor chip.

1.3 System power circuit and reset circuit

In this design, DC regulated power supplies of 5 V, 3.3 V, and 1.8 V are required. Among them, the 5 V power supply is generated by the LM317L three-terminal adjustable voltage regulator; the 3.3 V and 1_8 V power supplies are generated by the SPXlll7 with adjustable output voltage. The reliability of the system reset circuit plays a very important role in the stability of the entire system. The voltage monitoring chip TPS383K33 is used in the reset circuit, which is 10 ms or 200. ms optional power-on reset generator, with manual reset input function to prevent key jitter, allowing daisy chain voltage monitoring of multiple ICs, etc. The reset circuit is shown in Figure 2. In Figure 2, nRST is connected to the reset pin RESET of LPC2294; nTRST is connected to the reset pin of the Ethernet controller ENC28J60.

1.4 CAN bus interface

The CAN bus interface consists of LPC2294 and CAN bus transceiver. The high-speed CAN transceiver CTMl050T with isolation is used here. Its main function is to convert the logic level of the CAN controller into the differential level of the CAN bus. It also has (DC2500V) isolation function, ESD protection function and TVS tube to prevent bus overvoltage. Function, with built-in isolator, can reduce the design of external related circuits. The CAN bus interface circuit is shown in Figure 3. The CAN bus is connected to the physical bus through the two output terminals CANH and CANL of the CAN transceiver interface chip 82C250. The state of the CANH terminal can only be high level or suspended state, and the CANL terminal can only be low level or suspended state. This ensures that the phenomenon that occurs in the RS-485 network will not occur, that is, when there is an error in the system and multiple nodes send data to the bus at the same time, the bus will be short-circuited, thereby damaging some nodes. Moreover, the CAN node has the function of automatically shutting down the output in the case of serious errors, so that the operations of other nodes on the bus are not affected, thereby ensuring that the bus will not be in a "deadlock" due to problems with individual nodes in the network. state. Moreover, the complete communication protocol of CAN can be implemented by the CAN controller chip and its interface chip, thereby greatly reducing the difficulty of system development and shortening the development cycle. These are incomparable to RS-485 with only electrical protocol.

1.5 Ethernet interface

In the system design, ENC28J60 is used as the network interface chip. ENC28J60 is a 28-pin independent Ethernet controller launched by Microchip Technology of the United States. It has a built-in Ethernet physical layer device (PHY) and media access controller (MAC), and can reliably send and receive packet data according to the Ethernet protocol. In addition, it also has a programmable 8 KB dual-port SRAM buffer and a data transfer rate of up to 10 Mb/s. ENC28J60 has a variety of integrated functions, such as CRC check, programmable filtering, automatic evaluation, reception or rejection of various information packets, data filtering and other functions. It can store, retrieve and modify information packets efficiently, and can alleviate Controls the memory load of the main microprocessor. ENC28J60 uses a standard SPI serial interface, which can be connected to the microprocessor with only 4 wires, and it has only 28 pins, which can greatly simplify related designs and reduce space. The network socket uses RJ45 socket HR911102A, which has built-in network transformer, status display light and resistor network. It has the characteristics of signal coupling electrical isolation, impedance matching, interference suppression and other characteristics, which can improve the system's anti-interference ability and the stability of sending and receiving. The Ethernet interface circuit is shown in Figure 4. In Figure 4, the two interrupt pins INT and WOL of ENC28J60 are connected to EINTl and EINT2 of LPC2294 respectively; the SPI pins SO, SI, SCK and CS of ENC28J60 are respectively connected to the pins MISO1, MISll, SCKl and CSl of LPC2294, 2 dedicated pins. The pins (LEDA, LEDB) are used to connect to the LEDG and LEDY of HR911102A for network activity status indication.

1.6 External expansion memory interface

Since there is only 16 KB of RAM inside the LPC2294, which cannot meet the space requirements for Ethernet data storage, the design expands the external memory by 256 KB and uses RAMTRON's memory chip FM25256. FM25256 is a non-volatile memory manufactured using advanced ferroelectric technology. It has a much higher number of read and write operations than other non-volatile memories and can withstand more than one trillion read and write operations. The memory interface circuit is shown in Figure 5.