PLU programmable logic unit for creating small combinational and sequential logic circuits

When developing MCUs, some simple digital logic circuits are sometimes needed. The LPC804 and LPC55XX series integrate PLU (Programmable Logic Unit), a programmable logic unit, which can create small combination and sequential logic circuits to reduce costs.

Some customers have some questions about the concept and usage of PLU when using PLU. This article will explain this.

1. Introduction to PLU

The PLUs of LPC804 and LPC55XX are exactly the same in use. Contains 6 inputs, 8 outputs, 26 5-input lookup tables (LUTs), and 4 flip-flops (state Flip-Flops). 26 PLUs are connected to each other, and the outputs, lookup tables, and flip-flops are connected by Multiplexing, as follows:

Digital logic circuits are divided into combinational logic circuits and sequential logic circuits. Only sequential logic circuits require the use of flip-flops. When using a flip-flop, an external clock input needs to be provided to PLU_CLKIN. That is, no external clock is required when using a combinational logic circuit. An external clock is required when using a sequential logic circuit. as follows:

2. PLU configuration

Test the simplest combinational logic circuit and sequential logic circuit, as follows:

According to the pins of LPC55S69-EVK, they are as follows:

Configure the pins as follows:

Configure the clock. The CLKIN clock of the PLU is set to 10K input, as follows:

Configure the PLU peripherals as follows:

Configure the PWM peripherals and set the PWM to 50% duty cycle and 10K frequency, as follows:

3. PLU Configuration tool configuration

NXP has developed a PLU Configuration tool. This tool can generate corresponding codes based on digital logic circuits to configure the PLU and its truth table. The download link can be copied in the PLU peripheral configuration interface. The link is as follows:

https://www.nxp.com/mcu-plu-config-tool

3.1 Schematic configuration

Open the PLU configuration tool, select the schematic design, and do a simple OR operation and D flip-flop experiment, as follows:

Click File-》Export-》PLU source file in the menu bar to export it as a C file, and copy the contents of the C file into the main function, as follows:

/* LUT0 (or01) */
PLU->LUT[0].INP_MUX[0] = 0x00000003; /* IN3 (IN3) */
PLU->LUT[0].INP_MUX[1] = 0x00000004; /* IN4 (IN4) */
PLU->LUT[0].INP_MUX[2] = 0x0000003F; /* default */
PLU->LUT[0].INP_MUX[3] = 0x0000003F; /* default */
PLU->LUT[0].INP_MUX[4] = 0x0000003F; /* default */
PLU->LUT_TRUTH[0] = 0xeeeeeeee; /* or01 (or01) STD 2 INPUT OR */
PLU->OUTPUT_MUX[5] = 0x0000001a; /* FF0 (FF01) -> OUT5 */

The logic analyzer test results are as follows:

3.2 Verilog configuration

Open the PLU configuration tool, choose to import the verilog file, import the written .v file, and do a simple AND operation experiment, as follows:

Note that the trigger will only be used if posedge clock is declared in the verilog file, and negedge sys_rst_n cannot be used for reset. The posedge clock in the always statement will be replaced by the clock input of the CLKIN pin, so the clock pin has no effect. Copy the generated code into the main function and test it with a logic analyzer. The results are as follows: