Introduction to the microcontroller interrupt system_51 microcontroller interrupt system structure

What is an interrupt? It means interrupting what you are currently doing and moving on to something else. The microcontroller interrupt means that when the microcontroller is executing the program, suddenly a button is pressed (generating an external interrupt), and the microcontroller must process that button (interrupt response) to see what happened. After the button is processed Continue to return to program execution (interrupted return).

Structure of MCS-51 microcontroller interrupt system

The symbols, names and conditions of generation of the five interrupt sources are as follows.

INT0: External interrupt 0, introduced by the P3.2 port line, caused by low level or falling edge.

INT1: External interrupt 1, introduced by the P3.3 port line, caused by low level or falling edge.

T0: Timer/Counter 0 interrupt, caused by T0 overflowing and returning to zero.

T1: Timer/counter l interrupt, caused by T1 full return to zero.

TI/RI: Serial I/O interrupt, caused after the serial port completes the transmission/reception of a frame of characters.

The structural block diagram of the entire interrupt system is shown in Figure 1 below.

Figure 1 51 microcontroller interrupt system structure

As shown in the figure, it consists of special function registers related to interrupts, interrupt entrances, sequence query logic circuits, etc., including 5 interrupt request sources, and 4 interrupt control registers IE, IP, ECON and SCON to control interrupt types. Turn on and off interrupts and determine the priority of various interrupt sources.

Interrupt request source

(1) External interrupt request source: external interrupts 0 and 1, which are introduced through external pins. There are two pins on the microcontroller named INT0 and INT1, which are the two tubes P3.2 and P3.3. foot. There are four bits in the internal TCON related to external interrupts. IT0: INT0 trigger mode control bit, which can be set and reset by software. IT0=0, INT0 is a low-level trigger mode, IT0=1, INT0 is a negative transition trigger mode. The differences between these two methods will be discussed later. IE0: INT0 interrupt request flag bit. When there is an external interrupt request, this bit will be set to 1 (this is done by hardware). After the CPU responds to the interrupt, the hardware will clear IE0 to 0. The uses of IT1 and IE1 are the same as IT0 and IE0.

(2) Internal interrupt request source TF0: the overflow interrupt flag of timer T0. When T0 counts overflow, TF0 is set by hardware. When the CPU responds to the interrupt, TF0 is cleared to 0 by hardware. TF1: Similar to TF0. TI, RI: Serial port transmission and reception interrupts, which will be explained later in the serial port.

Interrupt enable register IE In the MCS-51 interrupt system, the enable or disable of interrupts is controlled by the on-chip bit-addressable 8-bit interrupt enable register IE. where EA is the master switch, if it is equal to 0, all interrupts are not allowed. ES - serial port interrupt enable ET1 - timer 1 interrupt enable EX1 - external interrupt 1 interrupt enable. ET0 - Timer 0 interrupt enabled EX0 - External interrupt 0 interrupt enabled. If we want to allow external interrupt 1, timer 1 interrupt is allowed, and others are not allowed, then IE can be EAX or 8CH. Of course, we can also use bit operation instructions

SETBEA

SETBET1SETBEX1