Assembly instructions (ARM architecture)

Common assembly instructions

1. General registers and program counter in ARM state

(1) Registers used by each working mode in ARM state

(2) Current Program Status Register (CPSR)

N: Whether the result is a negative number

Z: Whether the operation result is 0

C: Carry/borrow/shift overflow

V: Overflow flag (Overflow)

I: Interrupt disable bit

F: Fast interrupt disable bit

T: CPU status bit; when set, the CPU is in Thumb state; otherwise, it is in ARM state.

M4~M0: working mode bits

Interrupt disable bit: I bit and F bit belong to interrupt disable bit. When they are set, IRQ interrupt and FIQ interrupt are disabled respectively.

2. The representation format of ARM instructions in the machine is represented by 32-bit binary numbers.

There is an instruction in ARM: ADDEQS R0,R1,#8;

ARM instructions are divided into 5 domains:

The first field: the 4-bit [31:28] condition code field. There are 16 combinations of 4-bit condition codes.

The second field: instruction code field [27:20], in addition to the instruction code, also contains several very important instruction features and the encoding of the optional suffix.

The third field: address base Rn, is 4 bits [19:16], encoding 16 registers from R0 to R15.

The fourth field: the target or source register Rd, is 4 bits [15:12], encoding 16 registers from R0 to R15.

The fifth field: address offset or operation register, operand area [11:0].

The 5 fields of the above instruction are 0000 0010 1001 0001 0000 0000 0000 1000, and the hexadecimal code is 0291008H. The function of the instruction is to add R1 and 8 and put the result into R0.

3. Branch instruction (jump):

One is to use a branch instruction; the other is to directly write the target address value to the program counter PC (R15).

By writing the jump address value to the program counter PC, any jump in the 4GB address space can be realized. Before the jump, the future return address value can be saved by combining the use of "MOV LR, PC" and other similar instructions, thereby realizing subroutine calls in the 4GB continuous linear address space;

When using branch instructions, the jump space is limited.

Assembly instruction format:

{} {S} ,{,}

The content in <> in the format is essential, and the content in { } can be omitted.

indicates the operation code

{} indicates the conditional domain for instruction execution, such as EQ, NE, etc.

{S} determines whether the execution result of the instruction affects the value of CPSR. If this suffix is ​​used, the result of the instruction execution affects the value of CPSR, otherwise it does not.

indicates the destination register

indicates the first operand, which is a register

{,} indicates the second operand, which can be an immediate value, a register, or a register shift operand.