Bare Metal Series——2440 Clock

My own summary:

1.2440 has two PLLs, UPLL and MPLL. UPLL is used for USB clock UCLK, and MPLL corresponds to FCLK, HCLK, and PCLK. When ARM starts, it directly uses the external crystal oscillator as the CPU clock, which corresponds to 12Mhz for 2440. Only after setting the three values ​​of the clock register MPS, the specific register PLLCON has been clearly stated below. After setting the frequency division register, the CPU clock uses the multiplied FCLK clock.

2. The CPU clock is the FCLK clock, HCLK is divided from FCLK, and PCLK is divided from HCLK. The specific division ratio needs to be set in register CLKDIVN, see the manual for details.

3. The system needs to set the clock first for it to work. The clock is the heart of the CPU and peripherals. When you do not set the clock, the CPU directly uses the external crystal oscillator, so some slow devices can work without setting the clock. When setting the clock, there is a CPU clock mode - fast bus mode and asynchronous clock mode. I have searched a lot of information but have not figured it out. I have some understanding that in fast bus mode and when HDIVN is not 0, the CPU uses the HCLK clock and can change the CPU clock but does not change the frequency of FCLK and PCLK.

The following is a repost from someone else:

The default working frequency of S3C2410 CPU is 12MHz. The PLL circuit can generate a higher frequency for CPU and peripheral devices. S3C2410 has two PLLs: MPLL and UPLL. UPLL is dedicated to USB devices. MPLL is used for CPU and other peripheral devices.

MPLL generates three clock frequencies: FCLK, HCLK, and PLCK. FCLK is used for the CPU core, HCLK is used for AHB bus devices (such as SDRAM), and PCLK is used for APB bus devices (such as UART). The hardware using different clock frequencies can be seen from the clock structure diagram.

Figure 7-1. Clock Generator Block Diagram

(Note: It should be noted from the figure that Uart uses PCLK)

Clock source selection

Table 7-1 describes the correspondence between the mode control pins (OM3 and OM2) and the selected clock source. The state of OM[3:2] is latched by the state of OM3 and OM2 pins at the rising edge of nRESET (when the oscillator (crystal/oscillatto) clock output is stable, the nRESET pin becomes high).  

Note: 1. Although MPLL starts to be generated when the system is reset, it can only be used as the system clock after the MPLLCON register is effectively set. Before that, the external clock will be directly used as the system clock. Even if the initial value of the MPLLCON register does not need to be changed, the same value must be written into the register.

2. When OM[1:0] is 11, OM[3:2] is used to determine a test mode.

The following describes the MPLL startup process:

(Note: The following content is directly excerpted from "s3c2410 Complete Development Process", the Clock part is very well written)

The S3c2410 datasheet page 224, “Figure 7-4. Power-On Reset Sequence” shows the MPLL startup process after power-on.

Please follow the image of FCLK to understand the boot process:

1. A few milliseconds after power-on, the crystal oscillator output stabilizes, FCLK = crystal oscillator frequency, and after the nRESET signal returns to a high level, the CPU starts executing instructions.

2. We can start MPLL at the beginning of the program. After setting several registers of MPLL, we need to wait for a period of time (Lock Time) for the output of MPLL to stabilize. During this period of time (Lock Time), FCLK stops oscillating and CPU stops working. The length of Lock Time is set by the register LOCKTIME.

3. After the Lock Time, the MPLL output is normal and the CPU works under the new FCLK.

Setting the clock frequency of S3c2410 is to set several registers of MPLL:

1. LOCKTIME: set to 0x00ffffff

As mentioned above, after MPLL is started, it needs to wait for a period of time (Lock Time) to make its output stable. Bits [23:12] are used for UPLL, and bits [11:0] are used for MPLL. Use the default value 0x00ffffff.

2. CLKDIVN: used to set the ratio of FCLK:HCLK:PCLK, the default is 1:1:1

Here the value is set to 0x03, that is, FCLK:HCLK:PCLK=1:2:4

3. MPLLCON: set to (0x5c << 12)|(0x04 << 4)|(0x00), i.e. 0x5c0040

For the MPLLCON register, [19:12] is MDIV, [9:4] is PDIV, and [1:0] is SDIV. The calculation formula is as follows:

MPLL(FCLK) = (m * Fin)/(p * 2^s)

Where: m = MDIV + 8, p = PDIV + 2

Fin is the default input clock frequency of 12MHz. When MPLLCON is set to 0x5c0040, we can calculate FCLK=200MHz, and from the setting of CLKDIVN, we can know that: HCLK=100MHz, PCLK=50MHz.

Usually we write the clock initialization process as clock_init function for other functions to call. The code is as follows:

void clock_init(void)

{

        /*init clock*/

rLOCKTIME = 0xFFFFFF;

    /* Set FCLK:HCLK:PCLK=1:2:4. If the processor frequency is 200M, HCLK is 50M and PCLK is 25M. The ARM920T core uses FCLK, the memory controller, LCD controller, etc. use HCLK, and the watchdog, serial port, etc. use PCLK*/

rCLKDIVN = 0x3;

    /* Set the clock frequency to 200M*/

    rMPLLCON = 0x5c0040;

    }

Change the PLL frequency of 2410, the specific process is:

1. The first step of software work: Set the PMS divider control, that is, set the MPLLCON register.

For PMS, see Figure 7-2. There are certain rules for the setting of register MPLLCON. Not every Fclk frequency you want can be obtained. The official recommended table PLL VALUE SELECTION TABLE should be followed. Otherwise, you need to calculate it yourself according to the formula, but Mizi does not guarantee that your setting is appropriate. Therefore, if you want to work at 200MHz, just follow the recommended value of Vivi.

@ step1: set PMS divider control

        mov r1, #CLK_CTL_BASE

         ldr r2, =vMPLLCON_200

        str r2, [r1, #oMPLLCON]

    Among them, MDIV=0x5c, PDIV=0x04, SDIV=0x00. Formula Mpll (Fclk) = (m×Fin)/ (p×(2^s)) [m=MDIV+8, p=PDIV+2, s=SDIV]

2. The second step of software work: setting CLKDIVN.

This step is to set the frequency division coefficient, that is, Fclk is the CPU main frequency, Hclk is obtained by dividing Fclk, and Pclk is obtained by dividing Hclk. Assuming that Hclk is divided by two of Fclk, and Pclk is divided by two of Hclk, the frequency division coefficient ratio is Fclk: Hclk: Pclk = 1: 2: 4. Then Hclk is 100MHz, the bus clock cycle is 10ns, and Pclk is 50MHz.

@ step2: change clock divider

        mov r1, #CLK_CTL_BASE

        mov r2, #vCLKDIVN

        str r2, [r1, #oCLKDIVN]

3. The third step of software work: Supplementary settings of CLKDIVN

  void ChangeClockDivider(int hdivn,int pdivn)

{

     // hdivn,pdivn FCLK:HCLK:PCLK

     // 0,0 1:1:1

     // 0,1 1:1:2

     // 1,0 1:2:2

     // 1,1 1:2:4

    rCLKDIVN = (hdivn<<1) | pdivn;   

    if(hdivn)

        MMU_SetAsyncBusMode();

    else

        MMU_SetFastBusMode();

}

If HDIVN = 1, the CPU bus mode must be changed from fast bus mode to synchronous bus mode using the following command

;void MMU_SetFastBusMode(void)

; FCLK:HCLK= 1:1

  EXPORT MMU_SetFastBusMode

MMU_SetFastBusMode

   mrc p15,0,r0,c1,c0,0

   bic r0,r0,#R1_iA:OR:R1_nF

   mcr p15,0,r0,c1,c0,0

   MOV_PC_LR

If HDIVN=1 and CPU bus mode is fast bus mode, CPU is powered by HCLK. This feature can halve the CPU frequency without changing HCLK and PCLK.

;void MMU_SetAsyncBusMode(void)

; FCLK:HCLK= 1:2

   EXPORT MMU_SetAsyncBusMode

MMU_SetAsyncBusMode

   mrc p15,0,r0,c1,c0,0

   orr r0,r0,#R1_nF:OR:R1_iA

   mcr p15,0,r0,c1,c0,0

   MOV_PC_LR

4. The fourth step of software work: wait for the locktime time to make the new Fclk take effect

@ step4: stay locktime

        mov r1, #CLK_CTL_BASE

         ldr r2, =vLOCKTIME

        str r2, [r1, #oLOCKTIME]

6. Impact on peripherals

In this experiment, there are mainly two things that need to be changed, one peripheral is UART, and the other peripheral is SDRAM.

(1) UART, it is connected to the APB bus, so the corresponding clock signal is Pclk, which is currently 50MHz. If you want to set the baud rate to 115200bps, then according to the formula UBRDIV0=(int)(PCLK/(bps*16))-1, it should be 26. If you put it in the program, you should pay attention to the format. The details are as follows:

UBRDIV0 = ((int)(PCLK/16./UART_BAUD_RATE) -1);

(2) SDRAM, the main influencing factor is the refresh frequency. Previously, there was no detailed analysis on SDRAM, but now it can be explained in detail. Two HY57V561620CT-H chips are used. According to the manual, the refresh frequency is 8192 refresh cycles/64ms, so the refresh cycle is 64ms/8192 = 7.8125us. Look at the settings of each bit of the register REFRESH:

    REFEN[23]: Enable automatic mode, set to 1

    TREFMD[22]: Set to Auto refresh mode, set to 0

    ·Trp[21:20]: Check RAS precharge time. Check the SDRAM manual and find that the -H series parameter is at least 20ns. Now the clock cycle corresponding to Hclk is 10ns, so it should be at least 2 clocks. You can set it to 00

    Tsrc: Semi Row Cycle Time, also known as RAS Cycle Time, at least 65ms, so at least 6.5clock, according to the optional value, should be set to 11

    Refresh[10:0]:

    Formula refresh period = (2^11 - refresh_count +1)/Hclk, from which refresh_count = 2^11 + 1-refresh period * Hclk is derived. Substitute the value and calculate 1268 = 0x04f4. This value should be rounded to reduce the error.

    The remaining reserved values ​​are set to 0

It can be concluded that the value of this register should be 0x008c04f4.