ATmega88 Clock Source

The ATmega88 chip has the following clock sources that are selected by Flash fuses: The clock is input to the AVR clock generator and then distributed to the corresponding modules.

The different clock options are described in the following sections. Any clock source requires a high enough Vcc to start the oscillator and a minimum oscillation period to ensure that the power supply reaches a stable level before normal operation begins.

To ensure a high enough Vcc, the device remains in the internal reset state for a timeout delay (tTOUT) after the other reset sources are released. P37 "System Control and Reset" describes the start conditions of the internal reset. This delay (tTOUT) is timed by the watchdog oscillator, and the number of delay cycles is set by the fuse bits SUTx and CKSELx. Table 5 lists the optional delays. The frequency of the watchdog oscillator is determined by the operating voltage, see P283 "ATmega88 Typical Characteristics - Initial Data" for details.

The main purpose of the delay is to ensure that the AVR is in reset state before the system can provide the minimum Vcc that meets the application requirements. The MCU does not monitor the actual voltage during the delay process. Therefore, it is up to the user to choose a suitable delay time that is longer than the Vcc rise time. If this is not possible, an internal/external BOD should be used. The BOD circuit ensures that the Vcc is high enough before releasing the reset. The timeout delay can be disabled when using the BOD. We do not recommend disabling the timeout delay when the BOD circuit is not used.

The oscillator needs to oscillate for several cycles before the clock enters a stable state. A ripple counter inside the chip monitors the oscillator output clock and ensures that the internal reset is valid before a given number of cycles is reached. The counter then releases the reset signal and the device starts executing the program. The recommended oscillation startup time depends on the clock type and can be 6 cycles of an external clock to 32K cycles of a low-frequency crystal oscillator.

When the AVR chip starts from reset, the clock startup sequence includes the timeout delay and the startup time. After the CPU wakes up from power-down mode or power-saving mode, Vcc is considered high enough, so the startup sequence only includes the startup time.

Default clock source

The internal RC oscillator frequency of the ATmega88 device is calibrated to 8.0MHz when it leaves the factory and CKDIV8 is programmed to obtain a 1.0MHz system clock. The startup time is set to the longest and the timing cycle is enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). This setting ensures that the user can obtain the required clock source through any valid programming interface.